Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-08-11
2001-01-09
Tran, Minh Loan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S329000, C257S341000, C257S342000
Reexamination Certificate
active
06172398
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the structure and fabrication process of trenched DMOS power transistors. More particularly, this invention relates to a novel and improved structure and process for fabricating trenched DMOS power device. This device is provided with flexibly adjustable threshold voltage and punch through prevention by adjusting the doping concentration of a body-dopant redistribution-compensation region under a source region near a vertical channel along the trenched gate of the DMOS transistor cells.
2. Description of the Prior Art
A trenched power DMOS device may be troubled by a punch through problem generated due to an anomaly encountered during silicon diffusion. The anomaly is a phenomenon recognized as the body dopant redistribution. The redistribution phenomenon is characterized by a “distribution coefficient m” representing the ratio of the equilibrium concentration of the impurity in silicon to its equilibrium concentration in the oxide for the impurity in a Si—SiO2 system. When the distribution coefficient m for a particular impurity is less than one, then a process of growing an oxide layer drives the impurity from the silicon region to the silicon dioxide region. The values of the distribution coefficient m for boron are function of crystal orientation. At typical diffusion temperature, the value of m ranges from 0.15 to 0.3 for {100} silicon. Due to the fact that the distribution coefficient m is smaller than one,
FIGS. 1A and 1B
shows the distribution of the boron concentration in the interface of the silicon and the oxide. The redistribution of the boron, i.e., the equilibrium concentrations, when a slow diffusion process is applied is even more pronounced as that shown in
FIG. 1A
than that of a slow diffusion shown in FIG.
1
B.
Due to the redistribution of the boron ions when growing the gate-oxide, the body dopant concentration near the trenched gate is affected as that shown in
FIGS. 2A and 2B
.
FIG. 2A
is a cross sectional view of a trenched DMOS power device and
FIG. 2B
shows the net dopant concentration along two vertical line Y-Y′ and Z-Z′. It is clear that the body dopant concentration near the trenched gate Y-Y′ is lower than that along the line Z-Z′ by a redistribution reduction &dgr;P. With a low body dopant concentration near the trenched gate and the channel region, an early punch through is more likely to occur due to insufficient body dopant concentration near the channel regions.
Therefore, a need still exits in the art of power device fabrication, particularly for trenched DMOS design and fabrication, to provide a structure and fabrication process that would resolve the difficulties caused by the body dopant redistribution. More specifically, it is preferably that reduction of the body dopant concentration caused by this dopant redistribution can be properly compensated without requiring application of additional masks or complicated fabrication processes. Furthermore, it is desirable in compensating the dopant concentration, the threshold voltage can be flexibly controlled by adjusting the body dopant concentration near the channel region next to the trenched gate.
SUMMARY OF THE PRESENT INVENTION
It is therefore an object of the present invention to provide an improved trench DMOS structure, and fabrication process to overcome the aforementioned difficulties encountered in the prior art.
Specifically, it is an object of the present invention to provide an improved trench DMOS structure and fabrication process wherein the reduced body dopant concentration due to redistribution during the process of gate-oxidation near the trenched gate is properly compensated. This is achieved by performing a high-energy body dopant implant after the source implant before the source blocking mask is removed. A redistribution-compensation region is formed right under the source region such that the punch through difficulty caused by the redistribution is resolved.
Another object of this invention is to provid an improved trench DMOS device by forming a body-dopant redistribution-compensation region under the source region near the trenched gate. By carefully controlling the body dopant concentration near the trenched gate and the channel region, the threshold voltage can be adjusted for specific power device applications.
Another object of this invention is to provid an improved trench DMOS structure and fabrication process by performing a highenergy body dopant implant after the source implant before the source blocking mask is removed. A redistribution-compensation region is formed right under the source region such that the punch through difficulty caused by the redistribution is resolved. The punch through difficulty is therefore resolved without requiring the application of additional masks or employing more complicated fabrication processes.
Briefly, in a preferred embodiment, the present invention discloses a vertical DMOS transistor cell formed in a semiconductor substrate of a first conductivity type with a top surface and a bottom surface. The vertical DMOS transistor cell includes a trenched gate comprising polysilicon filling a trench opened from the top surface disposed substantially in a middle portion of the cell. The DMOS transistor cell further includes a source region of the first conductivity type surrounding the trenched gate near the top surface of the substrate. The DMOS transistor cell further includes a body region of a second conductivity type encompassing the source region. The body region surrounding the trenched gate and extends vertically to about one-half to two-third of the depth of the trenched gate. The body region further includes a body-dopant redistribution-compensation region under the source region near the trenched gate having a delta-increment body-dopant concentration distribution higher than remaining portions of the body region.
The present invention further discloses a method for fabricating a DMOS transistor on a substrate, which has a reduced gate-to-drain capacitance and improved gate-oxide integrity. The method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate; (b) performing a blank body implant with impurities of a second conductivity type followed by a body-diffusion process at an elevated temperature thus forming a body region surrounding the trenched gate; (c) applying a trench mask for etching a trench followed by removing the mask and depositing a gate filling material then removed the gate filling material from above the top surface of the substrate thus forming a trenched gate; (d) applying a source mask for performing source implant for forming a plurality of source regions; (e) performing a high energy body dopant implant to form a plurality of body-dopant redistribution-compensation region under the source region near the trenched gates followed by removing the source mask and applying an elevated temperature for diffusing the source regions and the body-dopant redistribution-compensation region thus forming a delta-increment body-dopant concentration region in said body region near the trenched gate; (f) depositing an insulation layer on top of the power device followed by applying a contact mask for opening a plurality of source and gate contact openings followed by removing the contact mask; and (g) depositing a metal layer and applying a metal mask for etching and defining the gate metal and source metal segments. In a preferred embodiment, the step (e) of opening a plurality of source and gate contact openings further includes a step (g1) of performing a low energy body dopant implant through the source and gate openings to form a shallow high concentration body dopant for reducing a source and gate contact resistance before removing the contact mask.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detaile
Hu Shouxiang
Lin Bo-In
MagePower Semiconductor Corp.
Tran Minh Loan
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