Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-30
2001-07-31
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S332000, C257S347000, C257S352000
Reexamination Certificate
active
06268625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a thin film transistor and a method for fabricating the same in which a seli alignment method is used to form an offset region and source and drain electrodes.
2. Discussion of the Related Art
A thin film transistor (hereinafter referred to as a TFT) is used in an SRAM cell of over 1M class instead of a CMOS load transistor or a load resistor. It is used as a switching device that switches picture data signals in each pixel. In particular, in case of an SRAM cell in which a PMOS TFT is used as a load transistor, off-current is reduced and on-current is increased so that the power consumption is diminished and that the memory characteristics are enhanced. Thus SRAM cells with good qualities can be realized.
An offset region is an important element for stable performance of an SRAM cell. It matters how precisely an offset region is formed. That is, the less it is modified in its process, the more precisely it is formed.
A conventional TFT and a conventional method for fabricating the same will be described with reference to the accompanying drawings.
FIG. 1
is a cross-sectional view showing the structure of a conventional TFT, which includes an insulating layer
21
, a gate electrode
22
a
formed on a predetermined area of the insulating layer
21
, a gate insulating film
24
formed on the insulating film
24
including the gate electrode
22
a
, a drain electrode D formed on the gate insulating film
24
and spaced apart from the gate electrode
22
a
, a source electrode S, in opposition to the drain electrode
22
a
, formed on the gate insulating film
24
to overlap the gate electrode
22
a
, and a channel region I and an offset region II formed on the gate insulating film
24
between the source electrode S and the drain electrode D. Herein, the offset region II is placed between the drain electrode D and the gate electrode
22
a.
A conventional method for fabricating the above-mentioned TFT will be described with reference to the accompanying drawings.
Referring initially to
FIG. 2A
, a first polysilicon layer
22
for a gate electrode of the TFT is formed on an insulating layer
21
. A first photoresist film
23
is coated on the first polysilicon layer
22
and is then patterned with an exposure and development process to form a pattern for a gate electrode.
Referring to
FIG. 2B
, thereafter, using this pattern as a mask, the first polysilicon layer
22
is selectively removed to form a gate electrode
22
a.
Referring to
FIG. 2C
, a gate insulating film
24
, which is a silicon oxide film, is deposited on the insulating layer
21
including the gate electrode
22
a
. Next, a second polysilicon layer
25
is formed on the gate insulating film
24
and then a second photoresist film
26
is coated on the second polysilicon layer
25
.
Referring to
FIG. 2D
, the second photoresist film
26
is patterned for formation of channel and offset regions so as to form a mask pattern
26
a
. Using the mask pattern
26
a
, impurity ions are implanted to form a source electrode S partially overlapping the gate electrode
22
a
and a drain electrode D spaced apart from the gate electrode
22
a
by a predetermined distance. Consequently, the overall process for fabricating the TFT is completed.
However, the conventional TFT and the conventional fabricating method thereof have the following problems. Since processes using masks are necessary in forming source and drain electrodes and channel and offset regions, the overall process becomes complicated. Further, in mask alignment, misalignment might be caused so that there is modified an offset region that is an important element for stable performance of an SRAM cell.
SUMMARY OF THE INVENTION
Therefore, the present invention is directed to a TFT and a fabricating method thereof that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a TFT and a method for fabricating the same in which a self-alignment method is applied using no masks in forming source and drain electrodes and offset and channel regions, so as to simplify the overall process and realize stable performance of SRAM cells.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the TFT includes a substrate; a trench formed in the substrate; an active layer formed on the substrate and on the trench; a gate insulating film formed on the active layer; a gate electrtode formed on the gate insulating film on at least one side of the trench; a source region formed in the active layer on a bottom side of the trench; and drain regions formed in the active layer on the substrate to be isolated form the gate electrode.
In another aspect of the present invention, a method for fabricating a TFT includes the steps of forming a trench having first and second sides in a substrate; forming an active layer on the substrate and on the trench; forming a gate insulating film on the active layer; forming first and second patterns of conductivity on the gate insulating film on the first and second sides of the trench and on the substrate adjoining to the first and second sides of the trench; implanting ions by using the first and second patterns as masks so as to form source and drain regions in the active layer; and removing the first and second patterns on the gate insulating film on the substrate so as to form first and second gate electrodes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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patent: 5270968 (1993-12-01), Kim et al.
patent: 5285093 (1994-02-01), Lage et al.
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patent: 5334862 (1994-08-01), Manning et al.
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patent: 5969378 (1999-10-01), Singh
patent: 6020600 (2000-02-01), Miyajima et al.
Shuji Idea et al., “A Polysilicon Transistor Technology for Large Capacity SRAMs”; International Electron Devices Meeting; Dec. 9-12, 1990; pp. 18.1.1-18.1.4.
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Ngo Ngan V.
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