Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-04
2002-04-30
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S332000, C257S565000
Reexamination Certificate
active
06380586
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a trench-type insulated gate bipolar transistor (hereinafter referred to as a “trench-type IGBT”) having a MOS gate, formed of a metal film, an oxide film and a semiconductor, buried in a trench in the surface portion of a semiconductor substrate.
BACKGROUND OF THE INVENTION
Insulated gate bipolar transistors (IGBT's) exhibit both the high breakdown voltage and high current characteristics of bipolar transistors and the high frequency characteristics of MOSFET's. Recently, the breakdown voltage and the capacity of the IGBT's have been increased, and some high power devices exhibiting a breakdown voltage of from 2500 to 4500 V and a current capacity of from several hundreds to 1800 A have been developed. These high power devices includes a module-type package or a flat package, in which multiple IGBT chips are mounted in parallel.
FIG. 19
is a cross sectional view of a conventional planar IGBT (hereinafter referred to as a “P-IGBT”). Referring now to
FIG. 19
, p-type well regions
2
are formed selectively from one of the major surfaces of a lightly doped (highly resistive) n-type drift layer
1
. In the surface portion of p-type well region
2
, n-type emitter regions
3
are formed selectively. A gate electrode
10
is formed above the extended portion of p-type well region
2
extended between n-type drift layer
1
and n-type emitter regions
3
with a gate oxide film
6
interposed therebetween. An emitter electrode
11
is in common contact with p-type well regions
2
and n-type emitter regions
3
. A p-type collector layer
4
is formed on the other surface of n-type drift layer
1
with a heavily doped n-type buffer layer
5
interposed therebetween. The n-type buffer layer
5
is doped more heavily than n-type drift layer
1
. A collector electrode
12
is in contact with p-type collector layer
4
.
Now the operation of the P-IGBT is explained. In the turn-on mode, an inversion layer (hereinafter referred to as a “channel”) is created in the surface portion of p-type well region
2
by applying a positive voltage higher than a certain threshold while collector electrode
12
is biased to be positive and emitter electrode
11
is biased to be negative (or grounded). Electrons are injected from n-type emitter region
3
to n-type drift layer
1
through the channel. The injected electrons lower the potential of n-type buffer layer
5
with respect to the potential of p-type collector layer
4
. When the forward voltage across the pn junction between n-type buffer layer
5
and p-type collector layer
4
exceeds the barrier layer voltage of about 0.6 V, holes are injected from p-type collector layer
4
to n-type drift layer
1
via n-type buffer layer
5
. The injected electrons and holes are accumulated in n-type drift layer
1
so that electrical neutrality may be realized. The accumulated electrons and holes modulate the conductivity of n-type drift layer
1
, resulting in a very low resistance of n-type drift layer
1
. The resulting very low resistance of n-type drift layer
1
switches the IGBT on. Hereinafter, the electrons and holes accumulated excessively in n-type drift layer
1
in the ON-state of the IGBT will be referred to as the “accumulated carriers”. The holes injected from p-type collector layer
4
in the ON-state pass p-type well region
2
and flow out from emitter electrode
11
in contact with p-type well region
2
.
The above described operation is the same with that of a pnp-transistor formed of a p-type collector layer
4
, an n-type drift layer
1
and a p-type well region
2
. The voltage drop between the collector and the emitter caused by a predetermined current (usually, the rated current) in the ON-state of the IGBT is called a “saturation voltage”.
In the turn-off mode, the channel between n-type emitter region
3
and n-type drift layer
1
vanishes as the positive voltage applied to gate electrode
10
is reduced. As the channel between n-type emitter region
3
and n-type drift layer
1
vanishes, the electron injection from n-type emitter region
3
stops, and the holes injected from p-type collector layer
4
to n-type drift layer
1
via n-type buffer layer
5
decrease. The accumulated carries in n-type drift layer
1
form pairs in n-type drift layer
1
and vanish. Or, the electrons flow out to collector electrode
12
via p-type collector layer
4
, and the holes flow out to emitter electrode
11
via p-type well region
2
. As all the accumulated carriers vanish, the resistance of n-type drift layer
1
becomes extremely high, resulting in an OFF-state of the IGBT. The loss caused during the period of transition from the ON-state to the OFF-state is called the “turn-off loss”.
As described above, the ON-state and the OFF-state of the IGBT are determined by the behaviors of the electrons and the holes in n-type drift layer
1
. When many carriers are accumulated in n-type drift layer
1
in the ON-state, the saturation voltage is low due to low resistance of n-type drift layer
1
. However, since the accumulated carriers are too many to remove in turning-off, the turn-off loss is large. When few carriers are accumulated in n-type drift layer
1
in the ON-state, the turn-off loss is small, since the accumulated carriers to be removed are few. However, the saturation voltage is high due to high resistance of n-type drift layer
1
.
Thus, there exists a tradeoff relation between the saturation voltage in the conductive state of the IGBT and the turn-off loss caused in turning-off of the IGBT, wherein the saturation voltage or the turn-off loss increases when the turn-off loss or the saturation voltage reduces. For applying IGBT's to semiconductor conversion apparatuses, it is important to reduce the tradeoff relation between the saturation voltage and the turn-off loss from the view point of reducing the heat loss.
Since the IGBT was invented in early eighties, various measures have been examined to reduce the tradeoff relation between the saturation voltage and the turn-off loss. Typical measures include a buffer layer disposed between a base layer and a collector layer, and a method of controlling the carrier life time in the base layer.
However, it is difficult to reduce the tradeoff relation between the saturation voltage and the turn-off loss only by changing the total amount of the electrons and the holes injected in n-type drift layer
1
. The tradeoff relation may be reduced by changing the distributions of the electrons and the holes injected in semiconductor substrate
1
. It has been pointed out for reducing the tradeoff relation that it is effective to increase the amount of the carrier accumulated on the side of the emitter electrode of the IGBT.
Recently, an IGBT (hereinafter referred to as a “T-IGBT”), that facilitates reducing the tradeoff relation by forming a MOS gate in a trench dug in the surface portion of a semiconductor substrate, has been proposed.
FIG. 20
is a cross sectional view of a conventional T-IGBT. Referring now to
FIG. 20
, p-type well regions
2
and n-type emitter regions
3
are formed from one of the major surfaces of a lightly doped n-type drift layer
1
. A trench
7
extends from the surface of n-type emitter region
3
to n-type drift layer
1
. A gate electrode
10
is buried in trench
7
with a gate oxide film
6
interposed therebetween. An n-type buffer layer
5
is on the other major surfaces of n-type drift layer
1
, and a p-type collector layer
4
is on n-type buffer layer
5
. An emitter electrode
11
is in common contact with n-type emitter regions
3
and p-type well regions
2
. A collector electrode
12
is in contact with p-type collector layer
4
.
The parameters of an exemplary T-IGBT, the rated voltage thereof is 4500 V and the rated current density thereof is 40 Acm
−2
, are as follows. The specific resistance of n-type drift layer
1
is about 320 &OHgr;cm. The thickness of n-type drift layer
1
is 490 &mgr;m. The depth of trench
7
is 6 &mgr;m. The short side length in the botto
Chaudhuri Olik
Fuji Electric & Co., Ltd.
Pham Hoai
Rossi & Associates
LandOfFree
Trench-type insulated gate bipolar transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Trench-type insulated gate bipolar transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench-type insulated gate bipolar transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2910938