Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-02-24
2001-03-13
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S332000, C257S336000
Reexamination Certificate
active
06201278
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET) uses a gate electrode to control an underlying surface channel joining a drain and a source. The channel, source and drain are located in a semiconductor substrate, with the substrate being doped oppositely to the source and drain. The gate electrode is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a patterned gate electrode as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate electrode and the source/drain regions.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon as the gate electrode in place of aluminum. Since polysilicon has the same high melting point as a silicon substrate, it can be deposited prior to source and drain formation, and serve as a mask during introduction of the source and drain regions by ion implantation. The resistance of polysilicon can be further reduced by forming a silicide on its top surface.
There is a relentless trend to miniaturize semiconductor dimensions. The number of IGFETs that can be manufactured on an integrated circuit chip can be increased by decreasing the horizontal dimensions. Resolution refers to the horizontal linewidth or space that a lithographic system can adequately print or resolve. Lithographic systems include optical projection and step and repeat equipment, and electron beam lithography equipment. In optical systems, for instance, resolution is limited by the equipment (e.g., diffraction of light, lens aberrations, mechanical stability), optical properties of the photoresist (e.g., resolution, photosensitivity, index of refraction), and process characteristics (e.g., softbake step, develop step, postbake step, and etching step).
Furthermore, scaling down the horizontal dimensions generally requires a corresponding decrease in the vertical dimensions. As IGFET vertical dimensions are reduced and the supply voltage remains constant (e.g., 3V), the maximum lateral electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. Reducing the electric field on the order of 30-40% can reduce hot-electron-induced currents by several orders of magnitude. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate electrode, and a heavy implant is self-aligned to the gate electrode on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bidirectional current is used), however LDD structures are typically formed for both the source and drain to avoid the need for an additional masking step.
In the manufacture of integrated circuits, the planarization of semiconductor wafers is becoming increasingly important as the number of layers used to form integrated circuits increases. For instance, the gate electrode and/or metallization layers formed to provide interconnects between various devices may result in nonuniform surfaces. The surface nonuniformities may interfere with the optical resolution of subsequent lithographic steps, leading to difficulty with printing high resolution patterns. The surface nonuniformities may also interfere with step coverage of subsequently deposited metal layers and possibly cause open circuits.
Accordingly, a need exists for an IGFET that can be manufactured with reduced horizontal dimensions, that preferably includes an LDD as well as a substantially planar top surface. It is especially desirable that the IGFET have a channel length that can be significantly smaller than the minimum resolution of the available lithographic system.
SUMMARY OF THE INVENTION
The present invention provides an insulated-gate field-effect transistor (IGFET) with a gate electrode in a trench (i.e., a trench transistor) and insulative spacers in the trench. A gate insulator is disposed on the bottom surface of the trench, the gate electrode is disposed on the gate insulator, and the insulative spacers are disposed between the gate electrode and opposing sidewalls of the trench. A source, drain and channel are adjacent to the bottom surface of the trench. Preferably, the channel is substantially aligned with the bottom surface of the gate electrode. If the trench length corresponds to the minimum resolution of a lithographic system, then the channel length is significantly smaller than the minimum resolution. Furthermore, lightly doped regions of the source and drain can be adjacent to the bottom surface of the trench, and the gate electrode can be substantially aligned with the top surface of the substrate. In this manner, a highly miniaturized IGFET can be produced.
A key feature of the invention is the use of insulative spacers in the trench that contact the gate electrode and are disposed between the gate electrode and opposing sidewalls of the trench.
Preferably, the source and drain include heavily doped regions adjacent to the top surface of the substrate. The insulative spacers can be disposed on the gate insulator which is disposed on the entire bottom surface, or alternatively, the insulative spacers can disposed on the bottom surface adjacent to the sidewalls and the gate insulator can be disposed on a central portion of the bottom surface between the insulative spacers. It is also preferred that substantially all of the gate electrode is within the trench, and that the channel length is less than half the trench length and less than 2000 angstroms. As exemplary materials, the gate electrode is polysilicon, the gate insulator is silicon dioxide, and the insulative spacers are silicon dioxide or silicon nitride.
Another aspect of the invention is a method of forming an IGFET. The method includes forming a trench in a substrate, forming insulative spacers in the trench, forming a gate insulator on the bottom surface of the trench, forming a gate electrode on the gate insulator and the insulative spacers, with the insulative spacers between the gate electrode and opposing sidewalls of the trench, and forming a source and drain adjacent to the bottom surface. The gate insulator can be formed eithe
Dawson Robert
Fulford Jr. H. Jim
Gardner Mark I.
Hause Frederick N.
Michael Mark W.
Advanced Micro Devices , Inc.
Crane Sara
Skjerven Morrill & MacPherson LLP
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