Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-07-18
1999-03-23
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257330, 257331, 257332, 257374, 257394, 257397, 257241, 257242, 257244, 257302, 438156, 438173, 438192, 438193, 438206, 438259, 438268, 438270, H01L 2170
Patent
active
058863826
ABSTRACT:
A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).
REFERENCES:
patent: 3805129 (1974-04-01), Pham-Ngu
patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 4740826 (1988-04-01), Chatterjee
patent: 4757029 (1988-07-01), Koury, Jr.
patent: 4890144 (1989-12-01), Teng et al.
patent: 4974060 (1990-11-01), Ogasawara
patent: 4982266 (1991-01-01), Chatterjee
patent: 5010386 (1991-04-01), Groover, III
patent: 5032882 (1991-07-01), Okumura et al.
patent: 5122848 (1992-06-01), Lee et al.
patent: 5140388 (1992-08-01), Bartelink
patent: 5158901 (1992-10-01), Kosa et al.
patent: 5243207 (1993-09-01), Plumton et al.
patent: 5285093 (1994-02-01), Lage et al.
patent: 5302846 (1994-04-01), Matsumoto
patent: 5308778 (1994-05-01), Fitch et al.
patent: 5308782 (1994-05-01), Mazure et al.
patent: 5324673 (1994-06-01), Fitch et al.
patent: 5327374 (1994-07-01), Krautschneider et al.
patent: 5378910 (1995-01-01), Yoshikawa
patent: 5398200 (1995-03-01), Mazure et al.
patent: 5408130 (1995-04-01), Woo et al.
patent: 5442214 (1995-08-01), Yang
patent: 5581101 (1996-12-01), Ning et al.
"High Performance Characteristics in Trench Dual-Gate MOSFET (TDMOS)," Mizuno et al; IEEE Transactions on Electron Devices, Sep. 1991.
"Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's," Takato et al; IEEE Transactions on Electron Devices, vol. 38, No. 3, Mar. 1991.
Abraham Fetsum
Motorola Inc.
Thomas Tom
Witek Keith E.
LandOfFree
Trench transistor structure comprising at least two vertical tra does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Trench transistor structure comprising at least two vertical tra, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench transistor structure comprising at least two vertical tra will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2128851