Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-30
2001-08-14
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S413000
Reexamination Certificate
active
06274905
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor devices and processing, and in particular to trench structures used in, for example, trench metal-oxide-semiconductor field effect transistors (MOSFETs), and methods of their manufacture.
FIG. 1
is a simplified cross section of a portion of an n-channel trench MOSFET. A trench
10
is lined with an electrically insulating material
12
, such as silicon dioxide, that acts as gate dielectric. It is then filled with a conductive material
14
, such as polysilicon, that provides the transistor gate terminal. The trench extends into an n-type drain region
16
which may be electrically contacted through the substrate of the device. A p-type well or body region
15
is formed on top of the substrate, and n-type source regions
18
are formed on either sides of trench
10
as shown. The active region of the MOS transistor is thus formed in channel region
20
adjacent to gate
14
and between source
18
and drain
16
.
Trench transistors are often used in power-handling applications, such as power supply management circuitry, hard disk drive circuitry, etc. Trench transistors may operate at 12-100 V, as compared to 2-5 V for a logic-type MOSFET. The gate of a trench transistor, which is proportional to the depth of the trench, is made relatively wide to improve the current-handling capability of the trench transistor. The section of the trench transistor shown in
FIG. 1
is often referred to as a cell because it contains one portion of the device that is repeated across the die. The trenches in, for example, power MOSFETs, are typically laid out in either a grid pattern,
25
as shown in
FIG. 2
, forming a closed cell configuration, a stripe pattern
30
, as shown in
FIG. 3
, forming an open cell configuration, or other type of patterns, such as a hexagonal pattern. With the substrate of the die acting as the common drain terminal for the cells, all source terminals are connected together and all gate terminals are connected together to form one large trench MOSFET.
For many applications a key performance characteristic of the trench MOSFET is its switching speed. To maximize the switching speed of the trench MOSFET it is desirable to minimize the resistivity of its gate material. As the die size for larger power MOSFETs and the length of trenches increases, the speed at which gate charge is distributed across the length of the trenches becomes a concern. To decrease the gate resistivity for the larger trench MOSFETs, trenches are typically divided into shorter segments and gate metal contact is distributed across the surface of the die.
FIG. 4
is a top view of a die showing gate and source wiring for a large trench power MOSFET of the open cell type. The gate which is typically made of metal (e.g. aluminum) includes bonding pad area
400
that receives bond wire
402
, and gate buses
404
that extend in parallel across the die. Gate buses
404
distribute the gate bias voltage to trenches
406
, only a few of which are shown for illustrative purposes. Accordingly, instead of relying on the gate material inside each trench, which is typically polysilicon, to propagate the gate bias voltage, metal buses
404
ensure faster and more uniform distribution of gate charge to the far end trenches across the die. Thus, gate buses
404
provide a low-resistance path from gate bonding pad
402
to the active gates across the die, improving the switching speed of the MOSFET.
The improved switching speed that is brought about by the busing of the gate electrode across the die, however, comes at the price of increased resistivity on the source electrode. This is because instead of having a single contiguous metal layer blanketing the top surface of the die, the source metal layer must be broken into several sections
408
to allow for gate busing. The higher source resistivity adversely impacts the MOSFET's drain-to-source on resistance R
DSon
, another speed-critical performance characteristic for power MOSFETs.
It is therefore desirable to produce a trench that is filled with low resistivity material for applications such as trench MOSFETs where lower gate resistivity and faster switching can be obtained without adversely impacting R
DSon
.
SUMMARY OF THE INVENTION
The present invention provides a trench structure that is substantially filled with refractory metal to form, for example, MOSFET gate terminals with low resistivity and fast switching speed. A trench transistor fabricated with the trench process according to the present invention exhibits lower gate resistivity for faster switching while maintaining low gate leakage current. The lower resistivity of the gate material eliminates the need for busing of the gate contact metal across the top surface of the die. This in turn allows for a single-square, contiguous source contact layer for optimum R
DSon
.
In a specific implementation, after the formation of the trenches and the gate dielectric layer, a buffer layer of, for example, polysilicon is formed over the gate dielectric layer. A refractory metal such as tungsten is then deposited over the buffer polysilicon layer using, for example, tungsten hexafluoride in a low-pressure chemical-vapor deposition (LPCVD) process. The buffer polysilicon layer relieves stress present in the gate dielectric layer and reduces gate leakage. The use of metal as the gate material reduces doping requirement for the buffer poly. This results in lower gate leakage current for n-channel trench MOSFETs and can eliminate problems associated with high energy implants such as boron penetration in p-channel trench MOSFETs.
Accordingly, in one embodiment, the present invention provides a trench structure including a trench formed in a substrate, a dielectric material lining at least a wall of the trench to form a dielectric layer, a buffer layer formed on the dielectric layer, the buffer layer having a first conductivity, and a high-conductivity layer formed adjacent to and electrically coupled to the buffer layer, the high-conductivity layer having a second conductivity greater than the first conductivity.
In a more specific embodiment, the present invention provides a trench metal-oxide-semiconductor field effect transistor (MOSFET) including a trench formed in a silicon substrate, a gate oxide layer lining side-walls and bottom of the trench, a polysilicon buffer layer lining the gate oxide layer, and a metal layer filling a center portion of the trench.
In yet another embodiment, the present invention provides a method for fabricating a trench structure in a substrate, the method including the steps of (a) forming a trench in the substrate; (b) forming a dielectric layer to line the trench; (c) forming a layer of buffer material on the dielectric layer to fill a first portion of the trench, the buffer material having a first electrical conductivity; and (d) filling a second portion of the trench with a high-conductivity material having a second electrical conductivity, the second electrical conductivity being greater than the first electrical conductivity.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the refractory metal gate trench MOSFET of the present invention.
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Fairchild Semiconductor Corporation
Loke Steven
Townsend and Townsend / and Crew LLP
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