Trench storage dram cell including a step transfer device

Details Trench storage dram cell including a step transfer device Trench storage dram cell including a step transfer device

1998-01-28

1998-11-03

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257301, H01L 27108, H01L 2976

Patent

active

058313010

ABSTRACT:
A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

REFERENCES:
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patent: 4890145 (1989-12-01), Malhi
patent: 5034787 (1991-07-01), Dhong et al.
patent: 5064777 (1991-11-01), Dhong et al.
patent: 5156992 (1992-10-01), Teng et al.
patent: 5198383 (1993-03-01), Teng et al.
patent: 5614431 (1997-03-01), DeBrosse
Nesbit, L., et al., "A 0.6 .mu.m.sup.2 256Mb Trench DRAM Cell with Self-Aligned BuriEd Strap (BEST), " IEDM 93, 1993, pp. 627-630.
Bronner, G., et al., "A Fully Planarized 0.25.mu.m CMOS Technology for 256Mbit DRAM and Beyond," 1995 Symposium on VLSI Technology Digest of Papers, pp.15-16.

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