Trench side wall charge trapping dielectric flash memory device

Details Trench side wall charge trapping dielectric flash memory device Trench side wall charge trapping dielectric flash memory device

2003-05-06

2004-06-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C257S324000

Reexamination Certificate

active

06754105

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a trench side wall charge trapping dielectric flash memory device, a corresponding core memory array and a method of operating the memory device.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual bit memory device, such as a charge trapping dielectric flash memory device
10
as illustrated in
FIG. 10
, can store data in a “double-bit” arrangement. That is, one bit can be stored using a first charge storing region
12
on a first “side” of the memory device
10
and a second bit can be stored using a second charge storing region
14
on a second “side” of the memory device
10
.
The charge storing regions
12
,
14
are part of a non-conductive charge trapping layer
16
that is disposed between a bottom (or tunnel) dielectric layer
18
and a top dielectric layer
20
. This dielectric stack can be formed over a P conductivity type substrate
22
having a first and a second bit line
24
disposed therein. A conductive word line
26
can be formed over the dielectric stack for serving as a gate electrode. The bit lines
24
can be formed from N conductivity type material and, upon application of appropriate voltages to the word line
26
and/or the bit lines
24
, the bit lines
24
can respectively function as a source and a drain with an active channel region
28
defined therebetween. In addition, by the appropriate application of voltage potentials to the gate electrode, the source and/or the drain, each charge storing region
12
,
14
can be programmed to store an amount of charge corresponding to a programmed, or charged, data state (as opposed to an unprogrammed, or blank, data state). The memory device
10
can also be read to determine the data state and can be erased by the appropriate application of voltage potentials to the gate electrode, the source and/or the drain.
Programming of the charge storage regions
12
,
16
involves channel hot electron (CHE) injection. For example, the first charge storing region
12
can be programmed to the charged data state by applying a voltage potential to the bit line
24
adjacent the first charge storing region
12
(such that this bit line
24
functions as a drain), applying a voltage potential to the word line
26
(such that the word line
26
functions as a gate electrode), and grounding the bit line
24
adjacent the second charge storing region
14
(such that this bit line
24
functions as a source). The source functions as a source of electrons for the CHE programming of the charge storing cell
12
.
The voltages applied to the gate electrode, the source and the drain generate a vertical electric field through the dielectric stack (layers
16
,
18
and
20
) and a lateral electric field along the length of the channel
28
from the source to the drain. At a given threshold voltage, the channel
28
will invert such that electrons are drawn off the source and begin accelerating toward the drain. As the electrons move along the length of the channel, the electrons gain energy and upon attaining enough energy, the electrons are able to jump over the potential barrier of the bottom dielectric layer
18
and into the charge storing layer
16
where the electrons become trapped. The probability of electrons jumping the potential barrier is a maximum in the area of the charge storing region
12
adjacent the drain, where the electrons have gained the most energy. These accelerated electrons are termed hot electrons and once injected into the charge storing layer
16
, stay in the charge storing region
12
of the charge storing layer
16
. The trapped electrons tend not to spread through the charge storing layer
16
due to this layer's low conductivity and low lateral electric field therein. Thus, the trapped charge remains localized in the charge trapping region
12
close to the drain
24
.
It is noted that the hot electrons must be diverted from their source to drain path in order to become injected in to the charge storing layer
16
. Typically, the injected electrons are scattered by phonons in the channel
28
such that these electrons are drawn upward by the vertical electric field mentioned above. The foregoing technique to program the first charge storing region
12
can be used to program the second charge storing region
14
, but the functions of the bit lines
24
(i.e., the source and drain functions) are reversed.
Programming one of the charge storing regions
12
,
14
to the charged data state using CHE involves a fairly high drain to source (I
ds
) current (e.g., on the order of about two hundred micro-Amps (&mgr;A)). Over the course of programming hundreds, thousands or even millions of memory devices
10
contained in a memory unit, a significant amount of power can be consumed. In addition, the ratio of injected electrons (i.e., those scattered electrons that are drawn upward and have enough energy to overcome the potential barrier of the bottom dielectric layer
18
and into the charge storing layer
16
as indicated by arrow
30
) to the total number of electrons traversing the channel
28
is fairly low. In other words, CHE can be a relatively inefficient process for a conventional memory device
10
.
In view of the foregoing, there is a need in the art for improved flash memory devices that can consume less power during programming and for improved methods of operating the flash memory devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a memory device. The memory device includes a semiconductor channel controlled by a gate electrode; a charge trapping region disposed laterally adjacent a first end of the channel; a first conductive region disposed adjacent the first end of the channel and functioning as a drain during programming of the charge trapping region, and a second conductive region disposed adjacent a second end of the channel and functioning as a source during programming of the charge trapping region, and wherein during programming of the charge trapping region electrons are drawn off the source and into the channel, the electrons traverse the channel from second end to first end and become energetic during the traversal so as to ballistically become injected into the charge trapping region through the first end of the channel.
According to another aspect of the invention, the invention is directed to a memory device. The memory device includes a) a first charge trapping region having at least a portion thereof disposed laterally adjacent a first end of a channel region and separated from the channel by a first tunnel dielectric region; b) a first select gate disposed laterally adjacent the first charge trapping region opposite the channel and separated from the first charge trapping region by a first select gate dielectric region; c) a second charge trapping region having at least a portion thereof disposed laterally adjacent a second end of a channel region and separated from the channel by a second tunnel dielectric region; d) a second select gate disposed laterally adjacent the second charge trapping region opposite the channel and separated from the second charge trapping region by a second select gate dielectric region; e) a control gate disposed over the channel and separated therefrom by a control gate dielectric; f) a first conductive region having at least a portion thereof disposed under the first end of the channel adjacent the first tunnel dielectric region; and g) a second conductive region having at least a portion thereof disposed under the second end of the channel adjacent the second tunnel dielectric region.
According to yet another aspect of the invention, the invention is directed to a core

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