Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-20
2004-11-23
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S329000, C257S331000, C257S332000, C257S341000, C257S381000
Reexamination Certificate
active
06822288
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to trench MOSFET devices, and more particularly to trench MOSFET devices having low source contact resistance.
A trench MOSFET (metal-oxide-semiconductor field-effect transistor) is a transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin insulator layer such as an oxide layer and filled with a conductor such as polycrystalline silicon (also known as polysilicon), allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench MOSFET transistors are disclosed, for example, in U.S. Pat. Nos. 5,072,266, 5,541,425, 5,866,931 and 6,031,265, the disclosures of which are hereby incorporated by reference.
As a specific example,
FIG. 1
illustrates half of a hexagonally shaped trench MOSFET structure
21
, which is disclosed in U.S. Pat. No. 5,072,266. The structure includes an n+ substrate
23
, upon which is grown a lightly doped n epitaxial layer
25
of a predetermined depth d
epi
. Within the epitaxial layer
25
, p body region
27
(p, p+) is provided. In the design shown, the p body region
27
is substantially planar (except in a central region) and typically lays a distance d
min
below the top surface of the epitaxial layer. Another layer
28
(n+) overlying most of the p body region
27
serves as source for the device. A series of hexagonally shaped trenches
29
are provided in the epitaxial layer, opening toward the top and having a predetermined depth d
tr
. The trenches
29
are typically lined with oxide and filled with conductive polycrystalline silicon, forming the gate for the MOSFET device. The trenches
29
define cell regions
31
that are also hexagonally shaped in horizontal cross-section.
A typical MOSFET device includes numerous individual MOSFET cells that are fabricated in parallel within a single chip (i.e., a section of a semiconductor wafer). Hence, the chip shown in
FIG. 1
contains numerous hexagonal-shaped cells
31
(portions of five of these cells are illustrated). Cell configurations other than hexagonal configurations are commonly used, including square-shaped configurations. In a design like that shown in
FIG. 1
, the substrate region
23
acts as a common drain contact for all of the individual MOSFET cells
31
. Although not illustrated, all the sources for the MOSFET cells
31
are typically shorted together via a metal source contact that is disposed on top of the n+ source regions
28
. An insulating region, such as borophosphosilicate glass (not shown), is typically placed between the polycrystalline silicon in the trenches
29
and the metal source contact to prevent the gate regions from being shorted with the source regions. Consequently, to make gate contact, the polycrystalline silicon within the trenches
29
is typically extended into a termination region beyond the MOSFET cells
31
, where a metal gate contact is provided on the polycrystalline silicon. Since the polycrystalline silicon gate regions are interconnected with one another via the trenches, this arrangement provides a single gate contact for all the gate regions of the device. As a result of this scheme, even though the chip contains a matrix of individual transistor cells
31
, these cells
31
behave as a single large transistor.
It has been found that, as the sheet resistance over the p-body increases, the voltage drop across the p-body also increases, making the parasitic NPN transistor more susceptible to being incidentally turned on. For example, during avalanche breakdown, the parasitic transistor can be activated incidentally, which can seriously degrade the overall performance of the device and can even cause permanent damage to the device.
One approach by which the resistance of the body region (and hence the voltage drop across the body region) can be decreased in a trench MOSFET device is illustrated in FIG.
1
. Within the cell region
31
, a p+ portion of the body region
27
rises to the top surface of the epitaxial layer and forms an exposed pattern
33
in a horizontal cross section at the top surface of the cell region
31
. This p+ central portion has a higher p-dopant concentration than the portion of the p-body region
27
that is adjacent the channel. This lowers the parasitic resistance of the P-body region
27
, improving the robustness of the transistor cell. This is achieved because the voltage drop across the body regions
27
of the device is reduced, likewise reducing the parasitic resistance and hence reducing the likelihood of incidentally turning on the parasitic NPN transistors.
(It is also noted that, for the specific design illustrated in
FIG. 1
, the p+ central portion of the p body region
27
extends to a depth d
max
below the surface of the epitaxial layer that is greater than the trench depth d
tr
for the transistor cell so that breakdown voltage tends to occur away from the trench surface and in the bulk of the semiconductor material.)
A similar approach through which the resistance of the body region can be decreased in a trench MOSFET device is described in U.S. Pat. No. 6,031,265.
FIG. 2
is taken from this patent and illustrates a portion of a trench MOSFET in which an N+ substrate
105
supports an N epi-layer
110
. Each transistor cell of this device includes a trenched gate
125
, an N+ source region
140
, and a P-body region
130
. An insulation layer
145
is also provided as is typical. Each transistor cell further includes a deep P+ region
138
formed in the P-body region. The deep P+ region
138
has a higher P-dopant concentration than the surrounding P-body, lowering the parasitic resistance of the P-body region
130
and improving the robustness of the transistor cell. A shallow P+ region
139
is further provided in the body region
130
to reduce the contact resistance at the metal contact
170
.
SUMMARY OF THE INVENTION
Unfortunately, the p+ regions in the upper portions of the p-bodies (e.g., exposed p+ pattern
33
in FIG.
1
and regions
139
in
FIG. 2
above) compete with the n+ source regions (e.g., regions
31
in FIG.
1
and regions
140
in
FIG. 2
) for contact area with the source contact (see, e.g., metal source contact
170
in FIG.
2
). This dearth of contact area is further exacerbated in the event that the die size shrinks or the cell density increases.
Moreover, during the process of forming the upper p+ portions of the body regions, diffusion of p-type species into the n-type source regions commonly occurs, reducing the n-dopant concentrations within the n-type source regions. Reduced n-dopant concentrations make it difficult to achieve an effective ohmic contact with the subsequently deposited metal contact. As a result, the contact resistance is increased.
Both of these effects (i.e., the decrease in contact area and the increase in contact resistance) combine to increase the overall drain-source resistance, Rd
ds
, of the device.
The present invention addresses these and other problems in the prior art. According to an embodiment of the invention, a trench MOSFET transistor device is provided, which comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body reg
Amato John E.
Hshieh Fwu-Iuan
So Koon Chong
Tsui Yan Man
Bonham, Esq. David B.
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Tran Minhloan
Tran Tan
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