Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-21
2003-12-02
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S341000, C257S342000
Reexamination Certificate
active
06657254
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to trench MOSFET devices, and more particularly to trench MOSFET devices with improved on-resistance.
A trench MOSFET (metal-oxide-semiconductor field-effect transistor) is a transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin insulator layer such as an oxide layer and filled with a conductor such as polysilicon (i.e., polycrystalline silicon), allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench MOSFET transistors are disclosed, for example, in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931, the disclosures of which are hereby incorporated by reference.
As a specific example,
FIG. 1
illustrates half of a hexagonally shaped trench MOSFET structure
21
disclosed in U.S. Pat. No. 5,072,266. The structure includes an n+ substrate
23
, upon which is grown a lightly doped n epitaxial layer
25
of a predetermined depth d
epi
. Within the epitaxial layer
25
, p body region
27
(p, p+) is provided. In the design shown, the p body region
27
is substantially planar (except in a central region) and typically lays a distance d
min
below the top surface of the epitaxial layer. Another layer
28
(n+) overlying most of the p body region
27
serves as source for the device. A series of hexagonally shaped trenches
29
are provided in the epitaxial layer, opening toward the top and having a predetermined depth d
tr
. The trenches
29
are typically lined with oxide and filled with conductive polysilicon, forming the gate for the MOSFET device. The trenches
29
define cell regions
31
that are also hexagonally shaped in horizontal cross-section. Within the cell region
31
, the p body region
27
rises to the top surface of the epitaxial layer and forms an exposed pattern
33
in a horizontal cross section at the top surface of the cell region
31
. In the specific design illustrated, the p+ central portion of the p body region
27
extends to a depth d
max
below the surface of the epitaxial layer that is greater than the trench depth d
tr
for the transistor cell so that breakdown voltage is away from the trench surface and into the bulk of the semiconductor material.
A typical MOSFET device includes numerous individual MOSFET cells that are fabricated in parallel within a single chip (i.e., a section of a semiconductor wafer). Hence, the chip shown in
FIG. 1
contains numerous hexagonal-shaped cells
31
(portions of five of these cells are illustrated). Cell configurations other than hexagonal configurations are commonly used, including square-shaped configurations. In a design like that shown in
FIG. 1
, the substrate region
23
acts as a common drain contact for all of the individual MOSFET cells
31
. Although not illustrated, all the sources for the MOSFET cells
31
are typically shorted together via a metal source contact that is disposed on top of the n+ source regions
28
. An insulating region, such as borophosphosilicate glass (not shown) is typically placed between the polysilicon in the trenches
29
and the metal source contact to prevent the gate regions from being shorted with the source regions. Consequently, to make gate contact, the polysilicon within the trenches
29
is typically extended into a termination region beyond the MOSFET cells
31
, where a metal gate contact is provided on the polysilicon. Since the polysilicon gate regions are interconnected with one another via the trenches, this arrangement provides a single gate contact for all the gate regions of the device. As a result of this scheme, even though the chip contains a matrix of individual transistor cells
31
, these cells
31
behave as a single large transistor.
Demand persists for trench MOSFET devices having ever-lower on-resistance. One way to decrease on-resistance is to decrease the thickness of the epitaxial layer. As a result, the region of the epitaxial layer lying between the body region and the substrate (see numeral
25
in
FIG. 1
) is reduced in thickness. Since this region is of relatively high resistivity, the on-resistance of the device is reduced. However, as is known in the art, the risk of breakdown increases as the epitaxial layer becomes thinner, particularly in the termination region, which is more vulnerable to breakdown.
SUMMARY OF THE INVENTION
According to an embodiment of the invention, a trench MOSFET device is provided. The device comprises: (a) a substrate of a first conductivity type (preferably an n-type conductivity silicon substrate); (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial region from an upper surface of the epitaxial layer; (d) an insulating layer (preferably an oxide layer) lining at least a portion of the trench; (e) a conductive region (preferably a doped polysilicon region) within the trench adjacent the insulating layer; (f) a doped region of the first conductivity type formed within the epitaxial layer between a bottom portion of the trench and the substrate, wherein the doped region has a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer; (g) a body region of a second conductivity type (preferably p-type conductivity) formed within an upper portion of the epitaxial layer and adjacent the trench, wherein the body region extends to a lesser depth from the upper surface of the epitaxial layer than does the trench; and (h) a source region of the first conductivity type formed within an upper portion of the body region and adjacent the trench.
The presence of the doped region lying between the bottom portion of the trench and the substrate (sometimes referred to herein as a “trench bottom implant” based on its preferred mode of formation) serves to reduce the on-resistance of the device. Preferably this region extends more than 50% of the distance from the trench bottom to the substrate, more preferably 100% of the distance from the trench bottom to the substrate.
According to another embodiment of the invention, a method of forming a trench MOSFET device is provided. The method comprises: (a) providing a substrate of a first conductivity type; (b) depositing an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) forming a body region of a second conductivity type within an upper portion of the epitaxial layer; (d) etching a trench extending into the epitaxial region from an upper surface of the epitaxial layer such that the trench extends to a greater depth from the upper surface of the epitaxial layer than does the body region; (e) forming a doped region of the first conductivity type between a bottom portion of the trench and the substrate such that the doped region has a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer; (f) forming an insulating layer lining at least a portion of the trench; (g) forming a conductive region within the trench adjacent the insulating layer; (h) forming a source region of the first conductivity type within an upper portion of the body region and adjacent the trench.
The doped region is preferably formed by a method comprising implanting a dopant of the first conductivity type into the epitaxial region, and diffusing dopant of the first conductivity type at elevated temperature. More preferably, the doped region is formed in connection with the trench by a method comprising: (a) forming a trench mask on the epitaxial layer; (b) etching the trench through the trench mask; (c) implanting a dopant of the first conductivity type through the trench mask; and (c) diffusing the dopant at elevated temperature. Even more preferably, the diffusion step is conducted co
Amato John E.
Hshieh Fwu-Iuan
So Koon Chong
Tsui Yan Man
Bonham, Esq. David B.
General Semiconductor Inc.
Loke Steven
Mansfield Esq. Heather L.
Mayer Fortkort & Williams PC
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