Trench isolation using doped sidewalls

Details Trench isolation using doped sidewalls Trench isolation using doped sidewalls

1994-08-26

1995-03-28

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257515, 257519, 257521, 257648, H01L 2704

Patent

active

054019982

ABSTRACT:
A P-type substrate is immersed in a solution of potassium hydroxide (KOH) which etches exposed portions of the substrate to form trenches with sidewalls at an angle of 54.7 degrees with respect to the top surface of the substrate. A vertical boron implant is then conducted which implants boron ions into the angled sidewalls of the trenches. A layer of oxide is then deposited over the substrate surface to fill the trenches approximately flush with the surface of the substrate. NMOS transistors may then be formed in the islands surrounded by the trenches so as to be isolated from other NMOS devices. The boron doping of the sidewalls prevents the inversion of the sidewalls due to any charged contaminants in the deposited oxide. This avoids parasitic leakage currents between the N-type source and drain regions of the NMOS transistors which abut the sidewalls of the trenches.

REFERENCES:
patent: 4498227 (1985-02-01), Howell
patent: 4507849 (1985-04-01), Shinozaki
patent: 4660278 (1987-04-01), Teng
B. Davari et al., "A Variable-Size Shallow Trench Isolation (STE) Technology With Diffused Sidewall Doping For Submicron CMOS," IEDM 88, pp. 92-95. Jan. 1988.
G. Fuse, et al., "A Practical Trench Isolation Technology With A Novel Planarization Process," IEDM 87, pp. 732-735. Jan. 1987.

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