Trench isolation structure having a low K dielectric encapsulate

Details Trench isolation structure having a low K dielectric encapsulate Trench isolation structure having a low K dielectric encapsulate

1997-12-19

1999-12-28

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438692, 438702, H01L 2176

Patent

active

060081090

ABSTRACT:
A process is provided for forming a trench isolation structure which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. As a result, the lateral width of the isolation structure may be decreased without significantly increasing the capacitance between those active areas. In an embodiment, a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner is thermally grown upon the sidewalls and base of the trench. A low K dielectric material is formed within the trench such that its upper surface is level with the upper surface of the substrate. A fill oxide is then formed across the upper surface of the dielectric material. The resulting trench isolation structure includes a low K dielectric material encapsulated by some form of oxide. The trench isolation structure is less likely to experience current leakage during the operation of an ensuing integrated circuit employing the isolation structure.

REFERENCES:
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5726090 (1998-03-01), Jang et al.
patent: 5753562 (1998-05-01), Kim
patent: 5888880 (1999-03-01), Gardner et al.
patent: 5909628 (1999-06-01), Chatterjee et al.

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