Trench isolation of field effect transistors

Details Trench isolation of field effect transistors Trench isolation of field effect transistors

1996-06-12

1998-07-07

Wallace, Valencia Martin

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 68, 257 71, 257372, 257382, 257509, 257510, H01L 2976, H01L 2994

Patent

active

057773700

ABSTRACT:
A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting when a metal silicide is used in the source/drain regions. A silicon wafer, is formed with a gate electrode material on a gate insulating layer before forming the trenches for isolation. Now, with an etch protective layer on the gate electrode, trenches are etched and filled with an insulating material in the gate electrode material, the gate insulating layer and the silicon wafer to isolate the active regions. After the gate electrode material is etched to define the gate electrodes, the tops of gate electrodes are in essentially the same plane as the tops of the trenches. Preferably in the fabrication process, sidewalls are formed on the walls of the trenches and the gate electrodes. This elevated trench structure prevents parasitic edge transistors and eliminates any possibly of junction leakage or shorting.

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