Trench isolation of a CMOS structure

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

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257369, 257374, 257397, 257403, 257407, 257412, 257 66, H01L 2120

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active

061147419

ABSTRACT:
An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).

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patent: 5661311 (1997-08-01), Takamura et al.
patent: 5721174 (1998-02-01), Peidous
patent: 5861104 (1999-01-01), Omid-Zohoor
patent: 5952701 (1999-09-01), Bulucea et al.

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