Trench isolation method of semiconductor device

Details Trench isolation method of semiconductor device Trench isolation method of semiconductor device

1999-09-23

2000-12-12

Chaudhuri, Olik

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

H01L 2176

Patent

active

061598232

ABSTRACT:
A trench isolation method is provided that prevents the formation of a dent between a trench isolation region and an active region and prevents the generation of water spots during a cleaning process. In the trench isolation method, an undercut is formed in a stress-relief oxide pad pattern formed below a nitride layer pattern that defines an active region as a mask pattern. A nitride liner, which is a stress-buffer layer, is then formed around the undercut such that is conforms to the shape of the undercut. Thus, even though the stress-buffer layer is partially etched during the removal of the nitride the hard mask pattern, the stress-buffer layer is not etched to a position below the upper surface of the substrate. Also, an anti-reflection layer, which is the main source of water spots, is simultaneously removed in the formation of the undercut.

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patent: 5578518 (1996-11-01), Koike et al.
patent: 5677231 (1997-10-01), Maniar et al.
patent: 5863827 (1999-01-01), Joyner
patent: 5963820 (1999-10-01), Jeng

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