Trench isolation method for semiconductor integrated circuit

Details Trench isolation method for semiconductor integrated circuit Trench isolation method for semiconductor integrated circuit

1999-07-01

2001-07-31

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S438000, C438S585000

Reexamination Certificate

active

06268265

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a trench isolation method for manufacturing a semiconductor integrated circuit.
2. Description of the Related Art
As the integration density of integrated circuits increases, the technology for forming an isolation region between the active regions becomes important. Trench isolation methods are widely employed for this purpose. In these methods, a trench is formed by etching at a predetermined area of a semiconductor substrate, and then the trench is filled with an insulating material. This increases the effective distance between adjacent transistors in active regions. The area of the isolation region is kept at a minimum by designing the trench to be deep and narrow. This is why the insulating material inside the trench is also called insulating film.
A prior art trench isolation method is now described with reference to
FIGS. 1 through 3
. Referring to
FIG. 1
, a pad oxide film, a pad nitride film, and a chemical vapor deposition (CVD) oxide film are sequentially formed on a semiconductor substrate
1
. A pad oxide film pattern
3
, a pad nitride film pattern
5
, and a CVD oxide film pattern
7
for exposing a predetermined area of the semiconductor substrate
1
are formed by continuously patterning the CVD oxide film, the pad nitride film, and the pad oxide film. A trench T is formed by etching exposed semiconductor substrate
1
using CVD oxide film pattern
7
as an etching mask.
Referring to
FIG. 2
, an insulating material filling the trench T is deposited on the entire surface of the resultant structure where the trench T is formed. The entire surface of the insulating film is etched until pad nitride film pattern
5
is exposed. A CMP process is widely used for this purpose. The insulating film has been formed into an insulating film pattern
9
.
Referring to
FIG. 3
, exposed pad nitride film pattern
5
and pad oxide film pattern
3
are removed. This exposes the active region of the substrate around the trench for further processing. Then insulating film pattern
9
is etched, forming an isolating film
9
a that has a recessed groove at an edge A.
The recessed groove exposes an upper comer of the trench accordingly, when a MOS transistor is later formed near the trench, a gate electric field caused by a gate voltage applied between a gate electrode of the MOS transistor and the substrate becomes disproportionately concentrated on the upper comer of the trench. As a result, even though a sub-threshold voltage is being applied to the gate electrode, a channel is nevertheless formed on a side wall of the trench. Accordingly, leakage current flows between a source area and a drain area of the MOS transistor. This phenomenon often occurs in MOS transistors having a narrow channel width. Also, the high concentration of electric field at the upper comer of the trench deteriorates the reliability of a gate oxide film.
SUMMARY OF THE INVENTION
To solve the above problem(s), it is an objective of the present invention to provide a trench isolation method by which the upper comer of the trench is not exposed.
To achieve the above objective, the present invention provides a method for manufacturing an integrated circuit device with a trench. A mask pattern is formed on a semiconductor substrate that exposes a predetermined area. A trench is formed by dry etching at the predetermined area, using the mask pattern as an etching mask. Then a thermal oxide film is formed on the side walls and the bottom of the trench, preferably by oxidation. This corrects local lattice damage from the dry etching process of forming the trench. A flowable oxide is then filled in the trench overflowing onto the mask pattern. Then a surface of the flowable oxide film is etched until the mask pattern is exposed, thereby forming a flowable oxide film pattern. Then the surface of the semiconductor substrate around the trench, i.e., the surface of the active region is exposed by removing the exposed mask pattern by a wet etchant. At this time the flowable oxide film pattern is also etched, thus forming a transformed flowable oxide film pattern having recessed grooves at the edge of the flowable oxide film pattern. Then thermal annealing is performed, which eliminates the grooves, and forms an isolation film covering the upper comer of the trench. The thermal oxide film prevents impurities of the flowing oxide from diffusing into the substrate.
The method of the invention avoids the recessed grooves and the exposed upper corners. Accordingly, devices with improved electrical characteristic can be formed in the active regions.


REFERENCES:
patent: 4740480 (1988-04-01), Ooka
patent: 5449640 (1995-09-01), Hunt et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5989978 (1999-11-01), Peidous
patent: 6040607 (2000-03-01), Wristers et al.
Stanley Wolf, “Silicon Processing for the VLSI Era”, vol. 3, pp. 224-225 and 371, 1995.

Affiliated with

Also associated with

Rating

Trench isolation method for semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trench isolation method for semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench isolation method for semiconductor integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2546806