Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-05-17
2005-05-17
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S396000, C257S397000, C257S398000, C257S399000, C257S400000, C257S510000, C257S519000, C257S647000, C257S648000
Reexamination Certificate
active
06894354
ABSTRACT:
An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
REFERENCES:
patent: 5536675 (1996-07-01), Bohr
patent: 5801083 (1998-09-01), Yu et al.
patent: 5874317 (1999-02-01), Stolmeijer
patent: 5915191 (1999-06-01), Jun
patent: 5969393 (1999-10-01), Noguchi
patent: 5994198 (1999-11-01), Hsu et al.
patent: 6034409 (2000-03-01), Sakai et al.
patent: 6081662 (2000-06-01), Murakami et al.
patent: 6087705 (2000-07-01), Gardner et al.
patent: 6154417 (2000-11-01), Kim
patent: 6171924 (2001-01-01), Wang et al.
patent: 6258688 (2001-07-01), Tsai
patent: 6274457 (2001-08-01), Sakai et al.
patent: 6342428 (2002-01-01), Zheng et al.
patent: 6350655 (2002-02-01), Mizuo
patent: 6355540 (2002-03-01), Wu
patent: 6380095 (2002-04-01), Liu et al.
patent: 6383931 (2002-05-01), Flanner et al.
patent: 01-282815 (1989-11-01), None
Shallow Trench Isolation Characteristics with High-Density-Plasma Chemical Vapor Deposition Gap-Fill Oxide for Deep-Submicron CMOS Technologies, Seung-Ho Lee et al., Jpn. J. Appl. Phys. vol. 37 (1998), pp. 1222-1227.
Impact of Shallow Trench Isolation on Reliability of Buried- and Surface-Chanel sub-μm PFET, William Tonti et al., 1995 IEEE. pp. 24-29.
Subbreakdown Drain Leakage Current in MOSFET, J. Chen et al., 1987 IEEE, pp. 515-517.
Shallow Trench Isolation for advanced ULSI CMOS Technologies, M. Nandakumar et al, Silicon Technology Development, Kilby Center, Texas Instruments, Undated, 4 pages.
Jono Keiji
Ueda Hirokazu
Watanabe Hiroyuki
KMT Semiconductor, LTD
Tran Thien F
Wells St. John P.S.
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