Trench insulation in substrate disks comprising logic...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C257SE21564

Reexamination Certificate

active

10530343

ABSTRACT:
Disclosed is a layer arrangement (4b,5b,9b,10, 9a,5a,4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insulating high-voltage power components (7) relative to low-voltage logic elements (6) that are integrated on the same chip (1, 2, 3). Also disclosed is the production of a sequence of alternating vertical layers in a trench (T). The electric strength for high voltages is improved while the influence of defects created by distortions of substrate disks is prevented.

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patent: 1184902 (2002-03-01), None

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