Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2007-09-18
2007-09-18
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257SE21564
Reexamination Certificate
active
10530343
ABSTRACT:
Disclosed is a layer arrangement (4b,5b,9b,10, 9a,5a,4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insulating high-voltage power components (7) relative to low-voltage logic elements (6) that are integrated on the same chip (1, 2, 3). Also disclosed is the production of a sequence of alternating vertical layers in a trench (T). The electric strength for high voltages is improved while the influence of defects created by distortions of substrate disks is prevented.
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Eckoldt Uwe
Lerner Ralf
Hunton & Williams LLP
Smith Matthew
X-Fab Semiconductor Foundries AG
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