Trench-gated vertical CMOS device

Details Trench-gated vertical CMOS device Trench-gated vertical CMOS device

1997-04-04

1999-01-26

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257329, 257347, 257351, 257369, 257374, 257466, H01L 2976, H01L 2994

Patent

active

058641580

ABSTRACT:
Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

REFERENCES:
patent: 4951102 (1990-08-01), Beitman et al.
patent: 5443992 (1995-08-01), Risch et al.
patent: 5581101 (1996-12-01), Ning et al.
patent: 5627097 (1997-05-01), Venkatesan et al.

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