Trench-gated MOSFET with bidirectional voltage clamping

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257342, 257331, 257155, H01L 27088, H01L 2947, H01L 2978

Patent

active

060491086

ABSTRACT:
The gate of a MOSFET is located in a lattice of trenches which define a plurality of cells. Most of the cells contain a MOSFET, but a selected number of the cells at predetermined locations in the lattice contain either a PN diode or a Schottky diode. The PN and Schottky diodes are connected in parallel with the channels in the MOSFET cells, with their anodes tied to the anode of the parasitic diodes in the MOSFET cells and their cathodes tied to the cathode of the parasitic diodes. When the MOSFET is biased in the normal direction (with the parasitic diode reverse-biased), the PN diodes provide a predictable breakdown voltage for the device and ensure that avalanche breakdown occurs at a location away from the trench gate where the hot carriers generated by the breakdown cannot damage the oxide layer which lines the walls of the trench. When the device is biased in the opposite direction, the Schottky diodes conduct and thereby limit charge storage at the PN junctions in the diode and MOSFET cells. This reduces the power loss in the MOSFET and improves the reverse recovery characteristics of the device when its bias is switched back to the normal direction.

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Masakatsu Hoshi, et al., "A DMOSFET Having A Cell Array Field Ring for Improving Avalanche Capability", May 18, 1993, Proceedings of the International Symposium on Power Semiconductor Devices and IC's (ISPSD), Monterey, May 18-20, 1993, pp. 141-145, XP000380145.

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