Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-29
2003-04-01
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S135000, C257S328000, C257S329000, C257S331000, C257S339000
Reexamination Certificate
active
06541817
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to trench-gate semiconductor devices, and particularly but not exclusively to trench-gate power MOSFETs which are insulated-gate field-effect devices. The invention also relates to methods of manufacturing such devices.
Trench-gate semiconductor devices are known, comprising a semiconductor body including a channel-accommodating region of a second conductivity type between source and drain regions of an opposite first conductivity type. The source region is adjacent a major surface of the body, from which surface a trench extends through the channel-accommodating region and into an underlying body portion between the channel-accommodating region and the drain region. A gate is present in the trench and capacitively coupled to the channel-accommodating region adjacent to a side wall of the trench between the gate.
An advantageous trench-gate semiconductor device is described in the ISPSD'98 paper “Simulated Superior Performances of Semiconductor Superjunction Devices” by T. Fujihira and Y. Miyasaka, pages 423 to 426 of the Proceedings of 1998 International Symposium on Power Semiconductor Devices & ICs, Kyoto. In this ISPSD'98 device the body portion comprises first regions of the first conductivity type interposed with second regions of the second conductivity type. This ISPSD'98 device is a particular embodiment of the advantageous general device type that was disclosed in United States patent specification U.S. Pat. No. 4,754,310 (our ref: PHB32740). The interposed first and second regions serve to carry a depletion layer from the drain region to the channel-accommodating region in an off state of the device and to provide parallel current paths along the first regions in a conducting state of the device. A significant improvement is obtained in the relationship between the on-resistance and breakdown voltage of the device, by providing these interposed regions instead of a single high-resistivity body portion as conventionally used. The whole contents of both the ISPSD'98 paper and U.S. Pat. No. 4,754,310 are hereby incorporated herein as reference material.
Published German patent application DE-A-197 36 981 describes the manufacture of other particular trench-gate device embodiments of this advantageous device type having interposed first and second regions. The whole contents of DE-A-197 36 981 are also hereby incorporated herein as reference material. In the manufacturing processes disclosed in DE-A-197 36 981, deep trenches are formed in the semiconductor body, to the depth of the drain region. Both the first and second regions are diffused regions formed at the lower part of the deep trenches by ion-implanting dopants of opposite conductivity types at opposite facing sidewalls of neighbouring trenches and then diffusing the implanted opposite-conductivity-type dopants until they meet to form a p-n junction in the intermediate body portion between the opposite facing sidewalls of the neighbouring trenches. The gate is formed in an upper part of the trench, capacitively coupled to the channel-accommodating region adjacent to a side wall of this upper part.
In practice, the device structures and processes disclosed in DE-A-197 36 981 can be difficult to implement in a volume-manufacturing and commercial context. It is difficult to ion implant dopants at the side walls of the lower part of narrow deep trenches, and so wider trenches than required for the trench-gate itself may be used. Furthermore some of the processes disclosed in DE-A-197 36 981 provide dielectric-filled trenches underneath the source, which may have an undesired effect in increasing the device cell area between neighbouring channels and hence increasing the on-resistance of the device.
SUMMARY OF THE INVENTON
It is an aim of the present invention to provide a trench-gate semiconductor device which is of the advantageous device type that comprises interposed first and second regions and which has a device structure that is particularly appropriate for obtaining a low on-resistance while permitting its manufacture using processes appropriate in a commercial volume-manufacturing context.
According to the present invention, there is provided a trench-gate semiconductor device having the features set out in claim
1
.
In trench-gate devices in accordance with the present invention, there are upper and lower parts to the trench. The trench-gate is present in an upper part, with the channel-accommodating region adjacent thereto. The relationship between on-resistance and breakdown-voltage of the device is improved by including the interposed first and second regions between the drain region and the channel-accommodating region, adjacent to a lower part of the trench. The first regions provide parallel current paths between the conduction channel and the drain region, and they are present between the second region and the side wall of the lower part of the trench. The doping concentration of the first conductivity type of the first region is higher than the doping concentration of the second conductivity type of the second region, so further reducing the on-resistance. However the charge of the space-charge region in the depleted body portion can still be adequately balanced because the width of the first region (measured perpendicular to the side wall of the trench) is made smaller than the width of the second region.
Such a construction is particularly appropriate for accommodating the first and second regions in a commercial trench-gate context, and it permits the device to have a low on-resistance due to the high doping concentration of the first regions that provide the parallel current paths between the conduction channel and the drain region. The high doping concentration of the narrow first region may typically correspond to a dopant diffusion profile from the lower part of the trench into a body portion that provides the second region. This device construction is convenient for commercial manufacture.
Thus, in accordance with another aspect of the invention, there is provided a method of manufacturing a trench-gate device wherein, into a body portion of the second conductivity type, dopant of the first conductivity type is out-diffused from the trench, through at least a side wall of a lower part of a trench so as to form the first region. The doping concentration of the second region is provided by the body portion of the second conductivity type, which may be typically an epitaxial layer having, for example, a uniform doping concentration of the second conductivity type. The diffused dopant of the first conductivity type (out-diffused from, for example, a doped layer in the trench) provides the first region with a doping concentration of the first conductivity type that is higher than the doping concentration of the second conductivity type of the body portion. Its diffusion depth (measured perpendicular to the side wall of the trench) is less than the remaining width of the body portion (measured perpendicular to said side wall) that provides the second region.
REFERENCES:
patent: 4754310 (1988-06-01), Coe
patent: 4914058 (1990-04-01), Blanchard
patent: 5064777 (1991-11-01), Dhong et al.
patent: 5378655 (1995-01-01), Hutchings et al.
patent: 5981996 (1999-11-01), Fujishima
patent: 6103578 (2000-08-01), Uenishi et al.
patent: 19736981 (1998-08-01), None
“Simulated Superior Performances of Semiconductor Superjunction Devices”, by T. Fujihira et al, Proceedings of 1998 International Symposium on Power Semiconductor Devices & Ics, pp. 423-426.
Hueting Raymond J. E.
Hurkx Godefridus A. M.
Biren Steven R.
Fahmy Wael
Koninklijke Philips Electronics , N.V.
Louie Wai-Sing
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