Trench-gate semiconductor devices and the manufacture thereof

Details Trench-gate semiconductor devices and the manufacture thereof Trench-gate semiconductor devices and the manufacture thereof

2002-11-12

2004-08-31

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257S344000, C257S347000

Reexamination Certificate

active

06784488

ABSTRACT:

The present invention relates to trench-gate semiconductor devices. More particularly, it concerns insulated gate field-effect power transistors (commonly termed “MOSFETs”) and the manufacture thereof.
Ideally, a power device would be able to switch between its “off-state” and “on-state” (and vice versa) with no power dissipation. However, substantial switching power losses occur in real power devices and there has always therefore been a desire to design the devices so as to minimise these losses, particularly for applications requiring high frequency switching.
The transient waveforms associated with a power MOSFET when the device is switched on and off are discussed for example in “Power Semiconductor Devices” by B. Jayant Baliga, pages 387 to 395 (hereinafter referred to as “Baliga”), the contents of which are hereby incorporated herein as reference material. Typical waveforms for such a device at turn-on when connected to an inductive load are schematically illustrated in
FIGS. 1A
to
1
C herein.
FIG. 1A
shows the gate-source voltage, Vgs,
FIG. 1B
the drain-source current, Ids, and
FIG. 1C
the drain-source voltage, Vds.
Three consecutive time intervals are shown in
FIGS. 1A
to
1
C, namely t
1
, t
2
and t
3
. It can be seen that a significant proportion of the power dissipation occurs during the intervals t
2
and t
3
. In t
2
, Vds is at its maximum blocking value and Ids rises, whilst in t
3
, Ids is relatively high and Vds falls from its maximum value. Similar waveforms are generated in reverse during turn-off.
It is an aim of the present invention to provide a trench-gate semiconductor device with reduced power losses and a method for manufacturing the device.
According to the invention, a trench-gate semiconductor device includes: a semiconductor body comprising a source region and a drain region of a first conductivity type, having therebetween a channel-accommodating region of an opposite, second conductivity type, the drain region comprising a drain drift region and a drain contact region, with the drain drift region between the channel-accommodating region and the drain contact region, and the drain drift region being doped to a lesser degree than the drain contact region; and an insulated gate provided in a trench, the trench extending through the channel-accommodating region into the drift region, wherein the drain drift region has a substantially intrinsic region below the trench, the substantially intrinsic region extending from the bottom of the trench, substantially across the drain drift region towards the drain contact region, such that when the drain-source voltage falls during turn-on of the device its rate of decrease is higher. This reduces the switching losses of the device.
The references herein to a higher rate of decrease and reduced switching losses are relative to an equivalent device without the substantially intrinsic region having instead material in conformity with the remainder of the drift region.
The invention further provides a method of manufacturing a trench-gate semiconductor device in a semiconductor body having a source region and a drain region of a first conductivity type, with a channel-accommodating region therebetween of a second conductivity type, and an insulated gate provided in a trench, the drain region comprising a drain drift region and a drain contact region, with the drain drift region between the channel-accommodating region and the drain contact region, and the drain drift region being doped to a lesser degree than the drain contact region, the method including the steps of:
(a) etching the trench through the semiconductor body into the drain drift region; and
(b) forming a substantially intrinsic region below the trench, which extends from the base of the trench, substantially across the drain drift region towards the drain contact region, such that when the drain-source voltage falls during turn-on of the finished device its rate of decrease is higher. This reduces the switching losses of the device.
The present invention yet further provides a method of manufacturing a trench-gate semiconductor device in a semiconductor body having a source region and a drain region of a first conductivity type, with a channel-accommodating region therebetween of a second conductivity type, and an insulated gate provided in a trench, the drain region comprising a drain drift region and a drain contact region, with the drain drift region between the channel-accommodating region and the drain contact region, and the drain drift region being doped to a lesser degree than the drain contact region, the method including the steps of:
(a) etching a groove through the semiconductor body, substantially through the drain drift region towards the drain contact region; and
(b) providing substantially intrinsic semiconductor material in a lower portion of the groove, defining the trench for the insulated gate in the upper portion of the groove, such that when the drain-source voltage falls during turn-on of the finished device its rate of decrease is higher.
The present invention is based on a development in understanding by the present inventors of the
FIG. 1C
characteristic. It is found that the fall of Vds during the time interval t
3
is in practice for all power MOSFETs not linear as illustrated, but drops rapidly in the initial part of t
3
, and then decays more slowly to a final value (equal to the product of the drain-source on resistance and the drain current). This waveform is shown schematically in FIG.
2
.
Vds falls at different rates during t
3
because the gate-drain capacitance (Cgd) is a function of voltage. Cgd can effectively be considered as two capacitors in series, one due to the gate oxide layer, and the other due to the depletion width in the silicon. At high values of Vds, the depletion width is wide and so'Cgd due to the depletion width is much smaller than Cgd due to the oxide layer. Therefore the total gate-drain capacitance is low. At low Vds values, Cgd is mainly dominated by the capacitance of the gate oxide. In t
3
, as shown in
FIG. 1A
, Vgs is substantially constant and thus the gate current, Ig, is approximately constant. Assuming that Ig is fixed, during t
3
, the rate of decrease of Vds is greater at high values of Vds because Cgd is lower, leading to a Vds waveform of the shape illustrated in FIG.
2
.
The inventors have devised a device configuration in which Vds falls even faster during the initial portion of t
3
, as substantial losses occur in the early part of t
3
, leading to a significant reduction in the switching losses at turn-on. In particular, the device includes a substantially intrinsic region at least below the trench. This serves to maintain a greater depletion width for longer during turn-on, therefore providing a lower value of Cgd for longer, which in turn leads to a faster decrease in the value of Vds during the initial part of t
3
. The steady-state on and off characteristics of the device are not significantly affected, because the main portion of the drift region retains its doping concentration (of the first conductivity type) over the main area of the device between gate trenches.
It will be appreciated that similar considerations apply to the converse situation of turn-off of the device. Initially, Cgd will be relatively high and so the rate of increase of Vds will be low. As the voltage increases, the depletion becomes wider and so Cgd decreases, thus increasing the rate of rise of voltage. During this phase, the presence of the substantially intrinsic region will result in a greater depletion width and a smaller Cgd at any given drain-source voltage than in a device without the substantially intrinsic region, so that Vds rises even more sharply than would otherwise be the case. Thus, the rate of increase of Vds is higher. This results in lower power losses at turn-off.
The substantially intrinsic region extends from the bottom of the trench, substantially across the drain drift region. Preferably, it extends at least halfway, or more preferably two thirds of

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