Trench-gate semiconductor devices

Details Trench-gate semiconductor devices Trench-gate semiconductor devices

2001-05-11

2003-07-01

Cuneo, Kamand (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C257S332000, C438S270000, C438S271000

Reexamination Certificate

active

06586800

ABSTRACT:

This invention relates to trench-gate semiconductor devices, for example power transistors, and to methods of manufacturing such devices.
Trench-gate semiconductor devices are known that comprise a semiconductor body having a plurality of transistor cells, wherein each transistor cell is surrounded by a trench-gate comprising a first trench extending into the semiconductor body with gate material in the trench and with an insulating overlayer on top of the gate material. Each transistor cell has an annular source region of a first conductivity type adjacent to the trench-gate, a channel-accommodating body region adjacent to the trench-gate under the source region, and a drain region of the first conductivity type adjacent to the trench-gate under the channel-accommodating body region. At least some of the transistor cells have a localised region of a second conductivity type, opposite to the first conductivity type, which is of higher conductivity than the channel-accommodating region, the localised region extending into the semiconductor body to the drain region and being separated from the trench-gate first trench by the channel-accommodating body region. A source electrode extends over said insulating overlayers and contacts the source regions and the localised regions.
The usual trench-gate semiconductor device of this known kind has a channel-accommodating body region in each transistor cell of the second conductivity type, opposite to that of the source and drain regions. One example is a vertical structure insulated-gate field-effect power transistor (commonly termed a “MOSFET”) in which the above-defined drain region is a high resistivity drain-drift region on a high conductivity substrate region of the same (first) conductivity type. Another example is vertical structure insulated-gate bipolar power transistor (commonly termed an “IGBT”) in which the above-defined drain region is a high resistivity drain-drift region on a high conductivity substrate region of the opposite (second) conductivity type. In a MOSFET or an IGBT as just described, the source, body and drain regions constitute a built-in parasitic bipolar transistor. Incidental turning on of this parasitc bipolar transistor may cause permanent damage to the trench-gate transistor cell and hence to the trench-gate device. The function of the above-defined localised region in these devices is to provide device ruggedness, that is to protect each cell having such a region against turning on of the parasitic bipolar transistor by having an avalanche diode current path from the drain region through the localised region to the source electrode.
A less usual trench-gate semiconductor device of said known kind is an accumulation-mode device, which has a channel-accommodating body region in each transistor cell of the game first conductivity type as the source and drain regions. In an insulated-gate such device (commonly termed an “ACCUFET”), the conductive channel induced by the trench-gate in the on-state is formed by charge-carrier accumulation. The function of the above-defined localised region in this device is to provide a depletion layer in the body region in the off-state which, together with a depletion layer from the insulated trench-gate may wholly deplete the channel-accommodating body region.
Conventional localised regions for both MOSFETS and ACCUFETS have dopant of the second conductivity type which is implanted from the semiconductor body top major surface and diffused to extend to the drain region. For a MOSFET the localised region preferably extends to below the depth of the surrounding trench-gate trench. A disadvantage of this conventional localised region is that vertical diffusion to the required depth of the localised region is necessarily accompanied by lateral diffusion, and the size of the transistor cell must be sufficiently large to ensure separation of the localised region from the surrounding trench-gate trench. It is desirable to have the transistor cell size small so that the trench-gate device hat high cell density and low specific resistance. Reduction of cell size is limited by the laterally diffused portion of this conventional localised region.
The disadvantage of conventionally formed localised regions as described above is recognised, for MOSFET transistors, in U.S. Pat. No. 5,895,951 (So et al). The whole contents of U.S. Pat. No. 5,895,951 are hereby incorporated herein as reference material. So et al proposes providing, within a vertical MOSFET cell, a deep trench having an insulating layer within the otherwise open trench, implanting dopant ions into the semiconductor body through the insulating layer in the trench, diffusing this implanted dopant into the semiconductor body, and filling the trench. The diffused dopant which has been implanted through the open trench forms the above-discussed localised region. Particular disadvantages of the So et al proposal are as follows. The high temperature diffusion anneals the implant damage and ensures that the implanted region meets up with body region of the transistor cell. However this diffusion limits how narrow the total trench plus implanted and diffused localised region can be. An added difficulty with the implantation process is that the deeper the trench the more it collimates the implanting beam, so that less of the dopant will tend to be implanted in the lower walls and bottom corners of the trench requiring extra diffusion to make up for this reduced implantation. Apart from these difficulties, since the localised region consists only of the comparatively narrow implanted and diffused dopant region outside the trench there will be a comparatively high electrical resistance of this localized region between where it contacts the source electrode and where it is under the bottom of the trench, whereas this path should have low electrical resistance to stop the parasitic bipolar transistor turning on.
An object of the present invention is to provide a trench-gate semiconductor device, and methods of manufacturing such a device, which device and methods overcome the above-discussed disadvantage of the conventional localised region while also avoiding the above-discussed disadvantages and difficulties associated with the U.S. Pat. No. 5,895,951 (So et al) proposal.
According to the present invention there is provided a trench-gate semiconductor device of the above-described kind, but that is characterised in that each said localised region comprises deposited semiconductor material of the second conductivity type which fills a second trench extending into the semiconductor body, with the source electrode contacting said localised region on the whole top area of the second trench. Such a device may have the features set out in claim 1. It may also have one or more of the advantageous preferred features set out in any one of claims
2
to
14
.
Every transistor cell of the device may have such a localised region comprising the deposited semiconductor material of the second conductivity type. Preferably each said localised region includes an out-diffused region extending from the side and bottom of the respective second trench, the out-diffused region having a diffusion profile of dopant from the deposited semiconductor material which fills the respective second trench.
The deposited high conductivity semiconductor material in the second trench, in accordance with the present invention, enables a well-defined sufficiently deep and narrow localised region for attaining a small size transistor cell. Where the device is a MOSFET, contact between the source electrode and the deposited semiconductor material on the whole top area of the second trench achieves the desired low electrical resistance path to the bottom of the second trench to stop the parasitic bipolar transistor turning on.
Where the localised region includes an out-diffused region of the deposited semiconductor material dopant extending from the side and bottom of the second trench, then this out-diffused region will extend a uniform distance from the second trench. Suc

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