Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-12
2001-07-03
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S330000, C257S331000
Reexamination Certificate
active
06255692
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a trench-gate semiconductor device including a region comprising a narrow-bandgap semiconductor material. In particular, the invention provides a trench-gate power semiconductor device such as, for example, an insulated-gate field-effect transistor (commonly termed a power MOSFET).
United States patent specification U.S. Pat. No. 5,698,869 discloses a trench-gate semiconductor device comprising a semiconductor body having a first major surface from which a trench-gate structure extends into the body. The body includes a body region of a first conductivity type which extends adjacent to the trench-gate structure. This body region provides the device with a channel-accommodating portion between first and second regions of an opposite second conductivity type in a current-carrying path of the device. The first region comprises a narrow-bandgap semiconductor material which is of the second conductivity type and of narrower energy bandgap than the semiconductor body so providing a heterojunction. The whole contents of U.S. Pat. No. 5,698,869 are hereby incorporated herein as reference material.
The devices disclosed in U.S. Pat. No. 5,698,869 have their body region at a floating potential, which in most cases is due to a so-called SOI (silicon on insulator) formation for the device. The inclusion of the narrow-bandgap semiconductor material suppresses this “floating body effect”, reducing leakage current across the device and improving drain breakdown voltage. Most embodiments in U.S. Pat. No. 5,698,869 are DRAM (dynamic random access memory) cells, the holding characteristics of which are improved by the inclusion of the narrow-bandgap semiconductor material in an interior of a drain region of the DRAM cell-select transistor. This drain region is formed adjacent to the trenched, first major surface of the semiconductor body. In these embodiments, the narrow-bandgap semiconductor material is formed in this region by ion implantation, and particularly by implantation of germanium ions into monocrystalline silicon.
SUMMARY OF THE INVENTION
The present invention is based on a recognition by the inventors that narrow-bandgap semiconductor material can be used advantageously in a new and particular manner, in the context of a trench-gate power semiconductor device to improve characteristics of the power device that are quite different from the characteristics of the devices of U.S. Pat. No. 5,698,869.
According to the present invention, there is provided a trench-gate semiconductor device which is a power device, and the trench-gate structure of which extends between the channel-accommodating portions of neighbouring side-by-side body regions of the device. These channel-accommodating portions are connected in parallel between a first main electrode (common to side-by-side source regions) and the second region (common to the side-by-side body regions). The narrow-bandgap material in this power device is doped to provide these source regions which form with the body regions a source p-n junction that comprises the heterojunction. This p-n heterojunction serves to suppress so-called “second breakdown”, which would otherwise result from the turning on of a parasitic bipolar transistor (formed by the body region of the first conductivity type between the first/source and second regions of the second conductivity type) in a high-current high-voltage condition between the first main electrode and the second region. This improves the safe operating area (SOA) of the power device, also termed its “ruggedness”.
A narrow-bandgap layer on the first major surface of the semiconductor body provides the side-by-side source regions outside the semiconductor body. The heterojunction acts in combination with the source p-n junction in such a way that the injection of charge carriers of the second conductivity type from the source regions into the body regions of the first conductivity type is very much lower than the injection of charge carriers of the first conductivity type from the body regions into the source regions. Thus, the parasitic transistor now has a very low gain.
If the device begins to approach a second breakdown condition in which an avalanche current of charge carriers of the first conductivity type begins to flow from the body regions into the source regions, then the current flow of charge carriers of the second conductivity type from the source regions into the body regions is suppressed by the p-n heterojunction, so avoiding turn-on of the parasitic bipolar transistor. As a result, the body regions can have a low doping concentration of the first conductivity type, without their doping needing to be locally increased to suppress the gain of the parasitic bipolar transistor. The layout geometry of this power device can be compact. Its manufacture can also be simplified.
REFERENCES:
patent: 5451800 (1995-09-01), Mohammad
patent: 5473176 (1995-12-01), Kakumoto
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5703383 (1997-12-01), Nakayama
patent: 01196874A (1989-08-01), None
patent: 02184078A (1990-07-01), None
Biren Steven R.
Eckert II George C.
Lee Eddie C.
U.S. Philips Corporation
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