Trench-free buried contact for SRAM devices

Details Trench-free buried contact for SRAM devices Trench-free buried contact for SRAM devices

1998-04-23

2000-10-03

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257383, 257384, 257385, 257336, 257344, 257408, H01L 2976, H01L 2994, H01L 31062, H01L 31113, H01L 31119

Patent

active

061277061

ABSTRACT:
A buried contact structure on a semiconductor substrate in the present invention is as follows. A gate insulator is on a portion of the substrate and a gate electrode is located over the gate insulator. A gate sidewall structure is on the sidewall of the gate electrode. A lightly doped junction region in the substrate is under the gate sidewall structure. A doped junction region is in the substrate abutting the lightly doped junction region and is located aside from the gate insulator. A doped buried contact region is in the substrate next to the doped junction region. An interconnect is located over a first portion of the doped buried contact region.
The buried contact structure can further include a shielding layer over a second portion of the doped buried contact region. For forming more connections, the buried contact structure can further have a dielectric layer over the interconnect, the substrate, the gate sidewall structure, and the gate electrode. A interconnect structures are located in the dielectric layer and have electrical contacts with the interconnect and the gate electrode.

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Shye Lin Wu et al., Characterization of Thin Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon, IEEE Transactions on Electron Devices, vol. 43, No. 2, Feb. 1996, pp. 287-294.

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