Trench formation in semiconductor integrated circuits (ICs)

Details Trench formation in semiconductor integrated circuits (ICs) Trench formation in semiconductor integrated circuits (ICs)

2006-01-24

2006-01-24

Smith, Bradley K. (Department: 2891)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S400000, C438S424000

Reexamination Certificate

active

06989317

ABSTRACT:
A novel trench etching method for etching trenches of different depths which are self-aligned to one another is presented. The method comprises the steps of (a) creating first and second trenches of a same depth in a dielectric layer, wherein the second trench is wider than the first trench, (b) forming a conformal gapfill layer on top of the dielectric layer such that the conformal gapfill layer is thicker in the first trench than in the second trench, (c) etching back the conformal gapfill layer until a bottom wall of the second trench is exposed to the atmosphere while a bottom wall of the first trench is still covered by the conformal gapfill layer, (d) etching further into the dielectric layer via the second trench. As a result, the second trench is deeper than the first trench.

REFERENCES:
patent: 6444495 (2002-09-01), Leung et al.
patent: 2001/0036705 (2001-11-01), Nishida et al.
patent: 2004/0126986 (2004-07-01), Wise et al.

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