Trench filling and planarization process

Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board

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156643, 29576W, 427 94, 427 95, 430314, H01L 2176

Patent

active

046719709

ABSTRACT:
A process for forming planar trench oxide isolated integrated circuit devices. In particular, the process fills trenches of diverse widths, yet provides a final structure in which the narrow trench dielectrics, the wide trench dielectrics, and the active region surfaces are substantially coplanar. Furthermore, the process reduces the likelihood of creating voids in the narrow trenches. According to one practice, following the formation of the trenches in the substrate, successive layers of conformal silicon nitride, conformal polysilicon, and relatively conformal CVD oxide are formed to the relative depth of the trenches. A photoresist mask is then first selectively formed over the central regions of the wide trenches and then used as a mask during the anisotropic etch of exposed oxide. The underlying polysilicon layer serves as an oxide etchant stop, and also provides the material from which the next successive oxidation partially fills the previously etched regions with thermal silicon dioxide. A further planarizing layer of oxide is then formed by poly deposition and oxidation. The nitride layer underlying the polysilicon layer prevents oxidation of the substrate. Fabrication is concluded with a planarization to the level of the active regions, including an etch of the nitride layer over such active regions.

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patent: 4473598 (1984-09-01), Ephrath
patent: 4493740 (1985-01-01), Komeda
patent: 4506434 (1985-03-01), Ogawa et al.
patent: 4509249 (1985-04-01), Goto
patent: 4551911 (1985-11-01), Sasaki
patent: 4571819 (1986-02-01), Rogers

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