Trench field effect transistor with reduced punch-through suscep

Details Trench field effect transistor with reduced punch-through suscep Trench field effect transistor with reduced punch-through suscep

1995-02-10

1996-09-24

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257328, 257331, 257335, 257339, 257341, H01L 2976, H01L 2994

Patent

active

055583130

ABSTRACT:
To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater net P type dopant concentration. Due to the higher net dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough. To maintain a low R.sub.DSon, the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer upon which the lightly doped epitaxial layer is formed. This underlying relatively highly conductive layer may, for example, be either substrate or a more highly doped epitaxial silicon layer.

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