Trench fet with self aligned source and contact

Details Trench fet with self aligned source and contact Trench fet with self aligned source and contact

2006-05-16

2006-05-16

Flynn, Nathan J. (Department: 3663)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S329000, C257S330000, C257S341000, C257S342000, C438S259000, C438S589000

Reexamination Certificate

active

07045859

ABSTRACT:
A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

REFERENCES:
patent: 4767722 (1988-08-01), Blanchard
patent: 5614751 (1997-03-01), Yilmaz et al.
patent: 5744386 (1998-04-01), Kenney
patent: 5910669 (1999-06-01), Chang et al.
patent: 5998835 (1999-12-01), Furukawa et al.
patent: 6188104 (2001-02-01), Choi et al.
patent: 6194741 (2001-02-01), Kinzer et al.
patent: 6236099 (2001-05-01), Boden, Jr.
patent: 6351018 (2002-02-01), Sapp
patent: 6413822 (2002-07-01), Williams et al.
patent: 6437386 (2002-08-01), Hurst et al.
patent: 6534365 (2003-03-01), Kim et al.
patent: 6538280 (2003-03-01), Nakamura
patent: 11-031815 (1999-02-01), None
S. Wolf et al, “Silicon Processing for the VLSI Era”, vol. 1—Process Technology, Second Edition, Chapter 1, p. 1, Lattic Press, Sunset Beach, CA (2000); ISBN No.: 0-9616721-6-1.
S. Wolf et al, “Silicon Processing for the VLSI Era”, vol. 1—Process Technology, First Edition, Chapoter 5, p. 124, Lattic Press, Sunset Beach, CA (1986), ISBN No.: 0-961672-3-7.
B. Jayant Baliga, “Power Devices”, Chapter 4 in “Modern Semiconductor Device Physics”, Edited by S.M. Sze, John Wiley & Sons, Inc., New York (1998), ISBN No.: 0-471-15237-4, pp. 183-185, 211, 215 and 217.
Wolf, S., “Silicon Processing for the VLSI Era”, vol. 3—The submicron MOSFET, pp. 368-373 (ISBN: 0-961672-5-3), Lattice Press, Sunset Beach (CA) (1995).

Affiliated with

Also associated with

Rating

Trench fet with self aligned source and contact does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trench fet with self aligned source and contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench fet with self aligned source and contact will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3595771