Trench DRAM cell with vertical device and buried word lines

Details Trench DRAM cell with vertical device and buried word lines Trench DRAM cell with vertical device and buried word lines

2005-09-20

2005-09-20

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S265000

Reexamination Certificate

active

06946700

ABSTRACT:
A DRAM array having trench capacitor cells of potentially 4F2surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

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