Trench contact structure of silicon on insulator

Details Trench contact structure of silicon on insulator Trench contact structure of silicon on insulator

1998-05-21

2001-01-16

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S370000

Reexamination Certificate

active

06175135

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87104160, filed Mar. 20, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a structure of a trench contact structure of silicon on insulator (SOI), and more particular to a structure of a trench contact structure of SOI used in a Bipolar-Complementary-Metal-Oxide-Semiconductor (BiCMOS) device.
2. Description of Related Art
The technology of SOI is about a technology of isolation used in a complementary-metal-oxide-semiconductor (CMOS) device. Its characteristics is that an insulating layer, in general, made of silicon dioxide is formed closely under the surface of the substrate to isolate the CMOS device from the main silicon substrate. Therefore, because the CMOS area isn't connected to the substrate, latch-up happening on the transistors within the active area would disappear due to the routes causing latch-up such as source to subtrate or well to substrate having been disconnected by the insulating layer.
The SOI described in the above can be done by one of following methods like separation by implanted oxygen (SIMOX), bonded wafer (BW), or dielectric isolation (DI). The advantages of the technology of SOI in the fabrication of the integrated circuit is not only able to effectively restrain the happening of latch-up electrically on the CMOS transistors due to the parasitic bipolar effect but also able to increase the immunity of MOS device to the soft error induced by the at particles. In the fabricating procedures, due to the line width being allowed to be reduced, it would be easier for the fabrication and therefore the size of the parasitic capacitors and the device are reduced to be able to increase the speed of the operation of the circuit.
The idea of a BiCMOS device is to carry both bipolar transistors and CMOS transistors so that the parts of circuit needing the high speed of the operation and the high current such as the Input/Output (I/O) can be done by the bipolar transistors and the areas needing the high integration and the low consumption of power such as the array area can be made by the CMOS transistors.
A BiCMOS device is formed on a substrate, which carries the structure with SOI, and lets the gate of the CMOS transistor be electrically coupled to the base of the transistor, in that a low power-delay multiplier would be more efficient. To apply a low voltage on the gate of the CMOS transistor some area of the available area of the device is needed to make a contact window and to apply a low voltage on the substrate with SOI device an additional area is needed either. This would undermine the integration due to the consuming of the area.
FIG. 1
illustrates the top view of a scheme of a conventional BiCMOS device using the technology of SOI. Referring to
FIG. 1
a substrate
100
has a structure of SOI, wherein a gate
102
of the MOS and the source/drain regions
104
a
,
104
b
are formed on the substrate
100
. The gate
102
and the base
101
are interconnected to the metal layer
108
through the contact windows
106
b
and thus they are electrically coupled together. Moreover a doped area
110
on the substrate around the contact window
106
b
with the same type of dopant as used in the substrate but higher density is to give a better electrically coupled effect. The scheme as illustrated in the
FIG. 1
has a few drawbacks that it increases the needed area of the device and results in the decrease of the integration and the complexity in the fabricating procedures.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a trench contact structure filled by a metal layer to allow the substrate and the conductive layer of gate to be electrically coupled together so that the fabricating procedures would be significantly simplified and the integration would be increased either due to the smaller use of the needed area in the device.
In accordance with the foregoing and other objectives of the invention, a trench contact structure of SOI having a substrate carrying a buried-in oxide layer and a silicon layer covering on the buried-in layer includes a conductive layer of -ate forming on the substrate, a dielectric layer forming on device by a chemical vapor deposition (CVD) method and a metal plug penetrating the dielectric layer and the conductive layer of gate to reach the silicon layer of base but not through it. Thus, the metal plug, the conductive layer of gate and the silicon layer are coupled together. There is a doped area around the contact area between the surface of the silicon layer of base and the metal plug. This doped area has the same type of dopant as used in the silicon layer of base but has higher density.
In short conclusions, the invention by utilizing a metal plug to fill into the trench contact structure on a substrate with SOI structure allows the substrate layer, the conductive layer and the metal plug to be electrically coupled together to reduce the size of the device and complexity of the fabricating procedures.


REFERENCES:
patent: 5559368 (1996-09-01), Hu et al.
patent: 5717227 (1998-02-01), Kim
patent: 5780899 (1998-07-01), Hu et al.
patent: 5789790 (1998-08-01), Morishita et al.
patent: 5808346 (1998-09-01), Ueda

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