Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-15
2003-01-21
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S304000
Reexamination Certificate
active
06509599
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a trench capacitor having an insulation collar and a corresponding method of producing such a trench capacitor.
The invention of the instant application as well as the underlying problems will be explained with regard to a trench capacitor used in a DRAM memory cell. However, the invention is applicable to any type of trench capacitor. Memory cells are used in integrated circuits (ICs), such as, for example, random access memories (RAMs), dynamic RAMs (DRAMs), synchronous DRAMs (SDRAMs), static RAMs (SRAMs), and read-only memories (ROMs). Other integrated circuits contain logic devices, such as, for example, programmable logic arrays (PLAs), application-specific ICs (ASICs), mixed logic/memory ICs (embedded DRAMs), or other circuit devices. Usually a number of ICs will be produced in parallel on a semiconductor substrate, such as, for example, a silicon wafer. After processing the wafer, the wafer is divided up in order to separate the ICs into a number of individual chips. The chips are then packaged into end products, for instance for use in consumer products such as, for example, computer systems, cellular telephones, personal digital assistants (PDAs) and other products. For discussion purposes, the invention will be described with regard to forming an individual memory cell.
Integrated circuits (ICs) or chips use capacitors for storing electrical charges. One example of an IC, which uses capacitors to store charges, is a memory IC, such as, for example, a chip for a dynamic read/write memory with random access (DRAM). In this case, the charge state (“0” or “1”) in the capacitor represents a data bit.
A DRAM chip contains a matrix of memory cells which are connected in the form of rows and columns. The row connections are usually referred to as word lines and the column connections as bit lines. Reading data from the memory cells or writing data into the memory cells is realized by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains two diffusion regions separated by a channel above which a gate is arranged. Depending on the direction of the current flow, one diffusion region is referred to as the drain and the other as the source. The designations “drain” and “source” are used mutually interchangeably here with regard to the diffusion regions. The gates are connected to a word line, and one of the diffusion regions is connected to a bit line. The other diffusion region is connected to the capacitor. Applying a suitable voltage to the gate switches the transistor on. This enables a current flow between the diffusion regions through the channel in order to thus form a connection between the capacitor and the bit line. Switching the transistor off disconnects this connection by interrupting the current flow through the channel.
The charge stored in the capacitor decreases with time on account of an inherent leakage current. Before the charge has decreased to an undetermined level (below a threshold value), the storage capacitor must be refreshed.
Ongoing efforts to reduce the size of storage devices promote the design of DRAMs having an increased density and a reduced characteristic size, that is to say a smaller memory cell area. Components, such as capacitors, having a reduced size are used in order to manufacture memory cells, which occupy a smaller surface region. However, the use of smaller capacitors results in a reduced storage capacitance, which, in turn, can adversely affect the functionality and usability of the storage device. For example, sense amplifiers or read amplifiers require a sufficient signal l level for a reliable read-out of the information in the memory cells. The ratio of the storage capacitance to the bit line capacitance is critical in determining the signal level. If the storage capacitance becomes too small, this ratio may be too small to generate a sufficient signal. A smaller storage capacitance also requires a higher refresh frequency.
One type of capacitor that is usually used in DRAMs is a trench capacitor. A trench capacitor has a three-dimensional structure formed in the silicon substrate. An increase in the volume or the capacitance of the trench capacitor can be achieved by etching deeper into the substrate. In this case, the increase in the capacitance of the trench capacitor does not have the effect of enlarging the surface occupied by the memory cell.
A trench capacitor usually, contains a trench etched into the substrate. This trench is typically filled with n
+
-doped polysilicon, which serves as one capacitor electrode (also referred to as storage capacitor). Optionally, a second capacitor electrode, also referred to as “buried plate”, is formed by out-diffusion of n
+
-dopants from a dopant source into a region of the substrate which surrounds the lower portion of the trench. An n
+
-doped silicate glass, such as, for example an arsenic-doped silicate glass (ASG), serves as the dopant source in this case. A storage dielectric containing nitride is generally used to insulate the two capacitor electrodes.
A dielectric collar is produced in the upper region of the trench in order to prevent a leakage current from the capacitor connection with the buried plate. The storage dielectric in the upper region of the trench, where the collar is to be formed, is removed before the collar is formed. Removing the nitride prevents a vertical leakage current along the collar.
However, the removal of the upper region of the nitride layer creates pinholes at the transition between the lower part of the collar and the upper part of the storage dielectric. Such pinholes impair the quality of the storage dielectric and are a significant source for the charge dissipation or charge loss from the trench. This reduces the retention time or storage time of the trench capacitor and consequently impairs its functionality.
In order to prevent the format ion of pinholes, a two-stage trench etching process has been proposed. In this case, first of all the trench is partly etched by reactive ion etching (RIE) down to the depth of the collar. The reactive ion etching is selective with respect to the hard mask used for etching. The chemicals generally used for a reactive ion etching comprise for example N
3
/HBr/He/O
2
. An oxide layer is then deposited and etched in such a way that it forms the collar on the trench sidewalls. The reactive ion etching is selective with regard to silicon if, for example, the chemicals CHF
3
/He/O
2
, CHF
3
/Ar, C
4
F
8
/Ar or CF
4
are used. The remaining region of the trench is etched once the collar has been formed. The storage dielectric is then formed over the collar and the lower region of the trench sidewalls. This method eliminates the need for removing the upper region of the storage dielectric and hence the formation of pinholes.
Although such a two-stage trench formation process is helpful in preventing pinholes, the second reactive ion etching step for removing silicon can cause excessive erosion of the collar. Such an impairment of the collar causes leakage currents. Furthermore, the collar serves as an etching hard mask for the second reactive ion etching step for producing the trench. This creates a lower portion of the trench with a diameter equal to the internal diameter of the collar. Consequently, the lower region of the trench is smaller than the upper region, which has a diameter approximately equal to the external diameter of the collar. This however is undesirable since the capacitance of the capacitor is reduced.
A customary DRAM cell will be described with reference to
FIG. 6 and a
method for producing the DRAM memory cell according to
FIG. 6
will be described with reference to
FIGS. 7
a-g.
The trench capacitor according to
FIG. 6
contains a storage dielectric
164
, which is formed in a stepped fashion over the collar
168
. This eliminates the need for removing the upper region of the storage dielectric layer and avo
Dequiedt Odile
Faul Jürgen
Lamprecht Alexandra
Morhard Klaus-Dieter
Schrems Martin
Greenberg Laurence A.
Locher Ralph E.
Prenty Mark V.
Siemens Aktiengesellschaft
Stemer Werner H.
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