Trench capacitor with epi buried layer

Details Trench capacitor with epi buried layer Trench capacitor with epi buried layer

1998-04-06

2001-07-24

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000

Reexamination Certificate

active

06265741

ABSTRACT:

FIELD OF INVENTION
The invention generally relates to device and device fabrication and, more particularly, to a trench capacitor.
BACKGROUND OF INVENTION
Integrated circuits (ICs) or chips employ capacitors for charge storage purposes. An example of an IC that employs capacitors for storing charge is a memory IC, such as a dynamic random access memory (DRAM) chip. The level of the charge (“0” or “1”) in the capacitor represents a bit of data.
A DRAM chip includes an array of memory cells interconnected by rows and columns. Typically, the row and column connections are referred to as wordlines and bitlines, respectively. Reading data from or writing data to the memory cells is accomplished by activating the appropriate wordlines and bitlines.
Typically, a DRAM memory cell comprises a transistor connected to a capacitor. The transistor includes two diffusion regions separated by a channel, above which is located a gate. Depending on the direction of current flow between the diffusion region, one is referred to as the drain and the other the source. The terms “drain” and “source” are herein used interchangeably to refer to the diffusion regions. The gate is coupled to a wordline and one of the diffusion regions is coupled to a bitline. The other diffusion region is coupled to the capacitor. Applying an appropriate voltage to the gate switches the transistor on, enabling current to flow through channel between the diffusion regions to form a connection between the capacitor and bitline. Switching off the transistor severs this connection by preventing current flowing through the channel.
One type of capacitor that is commonly employed in DRAMs is the trench capacitor. A trench capacitor is a three-dimensional structure formed in the substrate. Typically, a trench capacitor comprises a deep trench etched into the substrate. The trench is filled, for example, with n-type doped poly. The doped poly serves as one electrode of the capacitor (referred to as the storage node). An n-type doped region surrounds the lower portion of the trench, serving as a second electrode. The doped region is referred to as a “buried plate.”
A conventional technique for forming the buried plate includes outdiffusing dopants into region of the substrate surrounding the lower portion of the trench. The dopant source is typically provided by a doped silicate glass such as, for example, arsenic doped silicate glass (ASG). ASG is formed from TEOS and organic precursors such as TEAS or TEOA. Such precursors, however, are difficult to deliver into a low pressure chemical vapor deposition (LPCVD) system which results in bad wafer uniformity due wafer depletion. To compensate for bad wafer uniformity, smaller batch sizes are used as compared to other LPCVD processes. Furthermore, the ASG the precursors are relatively expensive. These two factors create a high cost of ownership for the ASG deposition process.
The formation of the buried plate using ASG requires a number of complicated processing steps to integrate the ASG process into the flow of process steps for DRAM manufacturing. This also contributes to an increase in cost as well as increase risk of yield loss.
Fabricating ICs on p−/p+ substrates is sometimes desirable as their use result in increased yields. p−/p+ substrates, for example, provide protection against latch-up. Furthermore, p−/p+ substrates provide better gathering capabilities for metal impurities and are more resistant against thermal wafer distortion than p- substrates. However, conventional trench capacitors with buried plate are not compatible with p−/p+ substrates. This is because the dopant concentrations of the n-type buried plate and the p-type substrate are in about the same regime, thereby neutralizing each other. From the forgoing discussion, it is desirable to provide a trench capacitor with an improved buried plate.
SUMMARY OF INVENTION
The invention relates to an improved trench capacitor, such as one employed in a memory cell. In one embodiment, the trench capacitor is employed in a DRAM cell of, for example, a DRAM or an embedded DRAM chip. The trench capacitor comprises an epitaxial layer lining the lower portion of the trench. In one embodiment, the epitaxial (epi) layer is doped to serve as a buried plate of the capacitor. Above the epi buried plate is a dielectric collar. A node dielectric lines the collar and epi buried plate, isolating the storage node of the trench capacitor from the buried plate. An epi spacer layer may be provided to provide separation between the doped epi buried plate and the substrate. In an alternative embodiment, the epi layer is undoped.


REFERENCES:
patent: 5629226 (1997-05-01), Ohtsuki
patent: 5731226 (1998-03-01), Lin et al.
patent: 5945704 (1999-08-01), Schrems et al.
patent: 36310235A (1988-05-01), None
patent: 363102351A (1998-05-01), None

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