Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-14
2003-08-19
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S243000, C438S246000, C438S386000, C438S389000, C438S592000, C438S655000, C257S068000, C257S071000, C257S301000, C257S304000, C257S305000
Reexamination Certificate
active
06608341
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a trench capacitor and a corresponding fabrication method.
Integrated circuits (ICs) or chips, such as dynamic random access memory chips (DRAM), contain capacitors for storing a charge. In this case, the charge state in the capacitor represents a data bit.
A DRAM chip contains a matrix of memory cells which are provided in the form of rows and columns and are addressed by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is performed by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains two diffusion regions isolated by a channel which is controlled by a gate. Depending on the direction of current flow, one diffusion region is referred to as the drain region and the other as the source region. One of the diffusion regions is connected to a bit line, the other diffusion region is connected to the capacitor and the gate is connected to a word line. By the application of suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the diffusion regions through the channel is switched on and off.
The charge stored in the capacitor decreases over time on account of leakage currents. Before the charge has decreased to an indeterminable level below a threshold value, the storage capacitor must be refreshed. For this reason, these memory cells are referred to as dynamic RAM (DRAM).
U.S. Pat. No. 5,867,420 discloses trench capacitor formed in a substrate. The central problem in known types of DRAM is the production of a sufficiently large capacitance for the trench capacitor. This problem will be aggravated in the future by the advancing miniaturization of semiconductor components. The continuous increase in the integration density means that the area available per memory cell and thus the capacitance of the trench capacitor decrease ever further. An excessively low capacitance of the trench capacitor can adversely influence the functionality and usability of the memory device, since an excessively small quantity of charge is stored on it.
By way of example, sense amplifiers require a sufficient signal level for reliably reading out the information situated in the memory cells. The ratio of the storage capacitance to the bit line capacitance is crucial in determining the signal level. If the storage capacitance is too low, the ratio may be too small for generating an adequate signal.
A lower storage capacitance likewise requires a higher refresh frequency, because the quantity of charge stored in the trench capacitor is limited by its capacitance and additionally decreases due to leakage currents. If the quantity of charge falls below a minimum quantity of charge in the storage capacitor, then it is no longer possible for the information stored therein to be read out by the connected sense amplifiers, the information is lost and read errors arise.
One way of avoiding read errors is to reduce the leakage currents. Firstly, the leakage current can be reduced by a transistor; secondly, the leakage current can be reduced by a capacitor dielectric; and, finally, the leakage current can be reduced by a buried strap or a buried contact to a buried plate. An undesirably reduced retention time can be lengthened by these measures.
A trench capacitor is usually used in DRAMs. A trench capacitor has a three-dimensional structure which is formed in a silicon substrate. An increase in the volume and thus in the capacitance of the trench capacitor can be achieved by etching more deeply into the substrate. In this case, the increase in the capacitance of the trench capacitor does not cause the surface occupied by the memory cell to be enlarged. However, this method is also limited, since the attainable etching depth of the trench capacitor depends on the trench diameter, so that it is only possible to attain specific, finite aspect ratios.
As the increase in the integration density advances, the substrate surface available per memory cell decreases ever further. The associated reduction in the trench diameter inevitably leads to a reduction in the capacitance of the trench capacitor. If the capacitance of the trench capacitor is dimensioned from the outset to be so low that the charge which can be stored is insufficient for entirely satisfactory readout by the sense amplifiers connected downstream, then this results in read errors.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a trench capacitor which overcomes the above-mentioned disadvantages of the heretofore-known trench capacitors of this general type and which has an increased capacitance for the same trench diameter and the same trench depth. A further object of the invention is to provide a method of fabricating such a trench capacitor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a trench capacitor, including:
a substrate formed with a trench having a trench wall, the trench having an upper region and a lower region;
an insulation collar formed in the upper region of the trench wall;
a buried layer, the lower region of the trench at least partially extending through the buried layer;
a dielectric layer disposed at the trench wall in the lower region of the trench and at the insulation collar;
a conductive trench filling provided in the trench and serving as an inner capacitor electrode;
a conductive layer serving as an outer capacitor electrode, the conductive layer being disposed such that, in the lower region of the trench, the conductive layer is disposed between the substrate and the dielectric layer and, at the insulation collar, the conductive layer is disposed between the insulation collar and the dielectric layer; and
the conductive layer including a metal, a metal silicide or a metal nitride.
The idea underlying the present invention is using a conductive layer as an outer capacitor electrode. In conventional trench capacitors, the capacitor area is restricted to a lower region of a trench which lies below an insulation collar. By using the conductive layer in the lower region of the trench and on the insulation collar, the available area and thus the available capacitance is increased.
In one advantageous embodiment of the invention, a buried plate is formed in the substrate around the lower region of the trench, thereby improving the electrical contact between a buried well and the conductive layer.
In a further advantageous embodiment of the invention, the trench capacitor is doped below the surface of the substrate in the region of a buried strap, so that a buried contact is produced and advantageously electrically connects the buried strap or a trench filling to a source region of a transistor. The doping in the region of the buried contact may be introduced for example by implantation, plasma doping and/or gas phase doping or another suitable method.
In a further advantageous embodiment of the invention, the conductive buried strap is formed on the conductive trench filling, which forms the inner capacitor electrode. The advantage of this procedure resides in the greater flexibility in the production of the buried contact.
A further advantageous embodiment of the trench capacitor according to the invention provides the formation of an insulation web for insulating an upper region of the conductive layer. The insulation web has the task of preventing a charge transport from the conductive layer to the electrically interconnected conductive trench filling, the conductive buried strap and the buried contact. As a result, the retention time of the memory cell is advantageously lengthened and undesirable bit errors on account of leakage currents are prevented. In a specific embodiment, the insulation web is composed of an oxide, nitride or oxynitride.
A further advantageous embodiment of the invention provides for the conductive layer to be composed of silicon (doped or undoped
Greenberg Laurence A.
Ho Hoai
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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