Trench-capacitor-one-transistor storage cell and array for dynam

Details Trench-capacitor-one-transistor storage cell and array for dynam Trench-capacitor-one-transistor storage cell and array for dynam

1990-10-30

1993-03-30

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

365203, 257301, G11C 1134, H01L 2978

Patent

active

051989956

ABSTRACT:
Lightly Depleted PMOS (LDP) substrate-plate trench-capacitor (SPT) cell Array architecture is disclosed including three types of devices: An enhancement NMOS transistor (ENMOS) which has a n+ poly gate with a positive threshold voltage range, an enhancement PMOS transistor (EPMOS) having a p+ poly gate with a negative threshold voltage range, and a lightly depleted PMOS transistor (LDPMOS) having a p+ poly gate. The LDPMOS is used as the access transistor in the SPT cell with body biased at the power supply voltage VDD, and can also be used in the write drivers. A sense amplifier is included which is a CMOS cross-coupled latch. An n-well is biased at a lower voltage than VDD, such as (VDD--Vg) where Vg is the silicon bandgap, and the lower thresholds enhance faster sensing. The CMOS cross-coupled latch is activated by turning on latching devices. The bitlines are prevented from charging to greater than VDD--Vg, which could cause the array devices of unselected cells to conduct current and alter the stored low-voltage state of such cells.

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Trench Capacitor Cell with Double Diffused Structure for Megabit Dynamic RAMS by Yoneda et al. Japan Soc. Appl. Phys. Tokyo Japan 1986 Sym on VLSI.
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