Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-24
2004-06-29
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000
Reexamination Certificate
active
06756626
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a trench capacitor and to a method of producing a trench capacitor.
A conventional trench capacitor and a corresponding method of producing such a trench capacitor are disclosed in U.S. Pat. No. 6,018,174.
In integrated circuits (ICs), capacitors are generally used to store electrical charges. For example, the dynamic read/write memories (DRAMs) of memory ICs are each composed of a select transistor and a storage capacitor. The information is stored in the storage capacitor in the form of electrical charges. The memory states “0” and “1” correspond respectively to a positively and negatively charged storage capacitor. A memory IC generally has a matrix of such DRAM cells, which are wired in the form of rows and columns. The row connections are usually referred to as word lines and the column connections are referred to as bit lines. The select transistor and the storage capacitor in the individual DRAM cells are in this case interconnected in such a way that when the select transistor is driven via a word line, the charge on the storage capacitor can be read in and out via a bit line.
One focus in the development of the technology of memory ICs with DRAMs is the storage capacitor. In order to obtain an adequate read signal from this storage capacitor and to make it insensitive to &agr;-particles, a storage capacity of 20 to 40 fF is required. In order to ensure such an adequate storage capacity in the cell area of the DRAMs, which is decreasing continually from technology step to technology step, storage capacitors have therefore been developed which make use of the third dimension.
Such three-dimensional storage capacitors in DRAM cells are configured either as stacked capacitors or as trench capacitors. Capacitors are composed basically of two conductive layers which are provided one above the other and are separated by a dielectric intermediate layer. Stacked capacitors in DRAM cells are placed on the generally planar select transistors, a conductive capacitor layer having an electrical connection to the select transistor.
Alternatively, three-dimensional storage capacitors are configured as trench capacitors. Trench capacitors are normally produced in such a way that, first of all, deep trenches are etched into the semiconductor substrate. These trenches are then lined with a dielectric layer, for example a nitride, and are then filled with a capacitor electrode, also referred to as a “storage electrode,” for example an n
+
-doped polysilicon. In the semiconductor substrate, a second capacitor electrode, also referred to as a “buried plate”, is formed, for example by outward diffusion of n-doping atoms from a dopant source in the region around the lower portion of the trench. The select transistor of the DRAM cells is then usually produced on the planar semiconductor surface beside the trench capacitor. In this case, the select transistor generally has two highly doped diffusion regions which are separated by a channel region, one diffusion region being connected to a bit line of the DRAM via a contact layer. On the other hand, the other diffusion region is connected via a capacitor connecting region to the capacitor electrode, which is formed in the interior of the trench. The channel of the select transistor is additionally separated, by a gate dielectric layer, from a gate electrode layer, which is connected to a word line of the DRAM cell. A procedure of reading into and out from the DRAM cell is controlled by the word line in such a way that, by applying a voltage to the gate electrode layer, a current-carrying channel is produced between the diffusion regions of the select transistor, so that information in the form of charges can be read into and out from the capacitor electrode in the trench via the capacitor terminal.
In the upper region of the trench of the trench capacitor, adjacent to the storage dielectric, an insulation layer, a “collar,” is additionally formed. This collar is intended to prevent a leakage current arising between the capacitor terminal and the buried plate which forms the outer electrode of the trench capacitor. Such a leakage current would shorten the retention time of the charges in the trench capacitor considerably and, therefore, increase the necessary refresh frequency of the DRAM cell in an undesired manner. The collar in the upper region of the trench is generally produced as an isolating oxide or nitride layer, which must be sufficiently thick in order to prevent a possible parasitic transistor parallel to the trench. The thickness and the material of the collar are in this case determined by the operating voltage used for the select transistor and the material properties of the surrounding layers. In the case of DRAM cells produced by silicon planar technology, a layer thickness of typically 25 nm is necessary when oxide is used as the collar material, in order to raise the turn-on voltage of the possible parasitic transistor along the trench above the operating voltage of the select transistor. However, a collar formed with such a thickness in the upper region of the trench restricts the access to the storage electrode in the lower trench region by narrowing the trench diameter sharply and, in addition, makes its formation more difficult.
Because of the continuously increasing reduction in the size of the DRAM cells, the cell areas for the trench capacitor, and therefore also the trench diameters, decrease from DRAM generation to DRAM generation. In order to ensure a constant capacitor capacitance of 20 fF to 40 fF, even with a reduced trench diameter, there is the possibility of increasing the depth of the trenches, but in the meantime this also runs up against both technological and economic limits. Firstly, the production of increasingly deeper trenches with a simultaneously reduced trench diameter requires new and expensive etching processes, which permit a very high aspect ratio (ratio of column depth to column width). In addition, starting from a specific trench depth, a considerably prolonged etching time results, which increases the costs of the etching process significantly and makes the subsequent formation of the dielectric layer and of the electrode more difficult or impossible.
Alternatively and additionally to further deepening of the trenches, methods are therefore increasingly being used which permit the surface within the trench capacitor to be enlarged, in order in this way to ensure an adequate storage capacity. For example, in particular the trench is widened in a lower region through the use of an additional etching step, which means that the storage electrode area of the trench capacitor may be enlarged.
However, one problem in the development of the trench capacitors continues to be presented by the upper trench region, which cannot be widened because of the predefined cell area, and in which the dielectric collar for preventing the parasitic select transistor along the trench is formed. Since this collar is to have a substantially constant thickness, even in the case of future DRAM generations, because of the operating voltages used for the select transistors, increased narrowing of the connection between the inner storage electrode in the trench and the select transistor occurs and, in the extreme case, can lead to the connection being cut off.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a storage capacitor, and more specifically a trench capacitor structure with an insulation collar and a DRAM cell with such a trench capacitor, as well as a method for its production which overcome the above-mentioned disadvantages of the heretofore-known methods and devices of this general type and which, even in the case of a trench area of very small dimensions, avoids a leakage current between the capacitor terminal and the buried plate and also ensures a reliable electrical connection of the inner storage electrode in the trench.
With the foregoing and other objects in view there is provided, in
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