Trap and delay pulse generator for a high speed clock

Details Trap and delay pulse generator for a high speed clock Trap and delay pulse generator for a high speed clock

2000-01-31

2001-01-16

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S230080, C365S189050, C365S191000, C327S149000

Reexamination Certificate

active

06175526

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to electronic circuits and in particular to a synchronous random access memory having a trap and delay pulse generator for a high speed clock.
BACKGROUND OF THE INVENTION
Synchronous random access memory such as synchronous dynamic random access memory (SDRAM) are designed to operate in a synchronous memory system. All input and output signals, with the exception of a clock enable signal during power down and self refresh modes, are synchronized to an active edge of a system clock.
A SDRAM includes an arrangement of memory cells. Each memory cell comprises a storage capacitor for storing a data bit as a charge and an access transistor for accessing the charge. The data bit charge provides either a binary logic high (high) voltage or a binary logic low (low) voltage. Data is stored in the memory cells during a write mode and retrieved during a read mode.
Data is transmitted to and from the memory cells on signal lines, referred to as bit lines or digit lines. The digit lines are coupled to input/output (I/O) lines through I/O transistors used as switches. Each memory cell provides, through a true digit line, the logic state of its stored data bit to a corresponding I/O line. Each memory cell also provides, through a corresponding complimentary digit line, the complementary logic state of its stored data bit to a corresponding I/O complement line. The true digit line and corresponding complimentary digit lines are referred to collectively as a digit line pair.
The memory cells are typically organized as one or more arrays and each memory cell has an address identifying its location in its array. The array organization comprises a configuration of intersecting rows and columns. A memory cell is associated with each intersection. In order to read from or write to a memory cell, that memory cell must be selected, or addressed. A row decoder activates a word line in response to a specified row address. The activated word line turns on the access transistors for each memory cell of the row. A column decoder selects a digit line pair in response to a specified column address. For a read operation the selected word line activates the access transistors for all memory cells in the row, and the column decoder couples the selected digit line pair onto a corresponding I/O line pair.
As set forth above, SDRAM memory cells use storage capacitors to store data. A logical high, or logical “1”, is stored as a charge on the capacitor. When a clock pulse initiates a READ command for reading data, the digit line pairs are first equilibrated to the same voltage.
Charge from a particular memory cell is coupled, for example, onto a true digit line, resulting in a small differential voltage between the true digit line and its corresponding complimentary digit line. A sense amplifier senses the small differential voltage across the digit line pair, and further increases the voltage differential to full logic levels for communication to the corresponding I/O lines. The data propagates through I/O isolator transistors onto the I/O lines and into a helper flip flop (HFF). The HFF is a bistable latch which can be fired or strobed with minimum differential to develop full logic levels. The I/O isolator transistors provide resistance between the sense amplifier and the digit line pair. This resistance stabilizes the sense amplifier and speeds up the sensing operation. Once the data has passed through the I/O isolator transistors onto the I/O lines, the HFF amplifies the data to full logic levels used at an output data buffer.
Typically, a minimum amount of time is required to fully perform a READ command before a subsequent READ command is performed. In particular, the HFF requires a minimum voltage separation on the I/O lines to ensure amplification to correct logic levels on the I/O lines for communication to the output data buffer.
If a clock pulse expires while a memory device is currently performing a READ command, an error may occur if the needed voltage separation has not yet been reached and therefore the HFF has not yet been fired to amplify the data on the I/O line pair. In this case, information to be placed in the output data buffer for communication on an output line is not available. The problem is further compounded because the clock pulse triggering the subsequent READ command can arrive before the present READ command is completed.
Therefore, what is needed is a way to delay the clock pulse triggering the READ command until there has been sufficient time for the minimum necessary I/O separation to occur to allow the HFF to amplify to full logic levels the differential voltage placed on the I/O lines through the I/O isolation transistors. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to provide a trap and delay pulse generator for command signals triggered off of a high speed clock in order to allow proper timing for initiating back to back functions.
SUMMARY OF THE INVENTION
A trap and delay pulse generator for a high speed clock device comprises an input stage for receiving a clock pulse, an optional delay path for delaying the clock pulse, an enable circuit for outputting the clock pulse depending on whether a particular function is performed, a latch for latching the clock pulse, and a one-shot pulse generator for outputting a pulse. A pulse width test option is included for widening out the pulse provided by the one-shot pulse generator. A control line coupled to the one-shot pulse generator prevents the output of the pulse after the clock pulse has been latched if the particular function is not to be performed.
In one embodiment, a method of allowing a synchronous dynamic random access memory (SDRAM) to trigger a READ function even after the initiating clock pulse has expired. The method comprises the steps of receiving an externally generated signal triggered off of a high speed clock pulse, enabling the externally generated signal if the SDRAM is to perform a READ function, latching the externally generated signal, delaying the latched externally generated signal to ensure proper I/O line separation, and generating an output pulse for initiation of the READ function.
In another embodiment, a trap and delay pulse generator for a synchronous dynamic random access memory (SDRAM) comprises an input stage for receiving an externally generated signal triggered off of a high speed clock pulse, a delay path coupled to the input stage for receiving and delaying the externally generated signal, an enable circuit coupled to the delay path for receiving and passing through the externally generated signal when the SDRAM performs a READ function, a latch circuit having a delay element coupled to the enable circuit for receiving, latching and delaying the externally generated signal provided by the enable circuit, wherein delay of the externally generated signal ensures the SDRAM has proper separation of the I/O line pair before firing the HFF for the READ function, and a one-shot coupled to the latch for receiving the latched externally generated signal and generating an output pulse for initiation of the READ function. A SDRAM and a computer system incorporating the trap and delay pulse generator is also presented.
The trap and delay pulse generator is useful to high speed clock devices receiving a sequence of clock pulses when it is necessary to complete one function after its initiating clock has expired and where the completion of the first function may overlap a subsequent clock pulse. If a device is dependent upon completing an operation late in the clock cycle following a delay time and the clock pulse expires prior to completing the operation, then the device may not successfully complete the operation. The trap and delay pulse generator latches a clock signal and delays it with a subsequent delay element to ensure an operation is performed independent of the ex

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