Transpose address mode in general purpose DSP processor

Details Transpose address mode in general purpose DSP processor Transpose address mode in general purpose DSP processor

2000-09-19

2003-11-11

Kim, Hong (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S110000, C711S201000, C711S216000, C711S217000, C711S219000

Reexamination Certificate

active

06647484

ABSTRACT:

BACKGROUND
The invention relates to digital signal processing, and in particular to register-indirect addressing modes used in digital signal processing systems.
Digital signal processing (DSP) has become the best solution for many types of signal processing. DSP systems support applications such as speech coding and decoding in digital cellular phones, encryption/decryption used in secure communications, speech recognition for user interfaces, audio and video systems, data communication equipment such as modems, vision systems, image compression and decompression, beam forming, and spectral analysis. DSP processors—microprocessors with special digital processing capabilities—make some of these applications practical for the first time, and offer major advantages over analog processing systems such as insensitivity to environment and insensitivity to component tolerances, leading to more predictable system response or behavior. Some DSP systems have other advantages—the DSP processors are reprogrammable, in some cases in the field, to perform a variety of tasks without the need to use different electronic components. These types of advantages along with advances in integrated circuit manufacturing make DSP systems and processors rapidly growing areas of electronics.
A DSP system or processor performs mathematical operations to a sequence of samples of a physical signal, which have been first converted into a digital format, that is, a sequence of numbers. The samples can be obtained by a transducer such as a microphone and converted into digital format by an analog-to-digital converter. After mathematical processing occurs in the DSP system, a digital-to-analog converter can convert if desired the digital signals back into analog signals for use in the real world.
DSP systems share features to enable repetitive numerical computations. For example, the data path of DSP processors—where math manipulation of the signals takes place—is not used to calculate the addresses of the operands for instructions. Instead, DSP processors provide dedicated hardware referred to as an address generation unit to calculate addresses. The address generation units calculate the address while the data path performs math on the data, which improves processor performance. The address generation units are also capable of many types of addressing modes.
In register-indirect addressing mode, the data addressed are in memory, and the addresses of the memory locations are held in register(s). One form of register-indirect addressing uses modulo arithmetic to manage data buffers. A data buffer is a section of memory used to store data from off-chip or from prior calculations until the processor is ready to process the data. Because memory is a resource, the program only allocates some of the memory for use as a buffer. Some DSP systems manage data flow into the buffer by a first-in-first-out (FIFO)—the data is read from the buffer in the same order it arrived. To manage the FIFO buffer, the program includes a read pointer and a write pointer in a register. The read pointer points to (i.e., contains the address of) the memory location where the next data will be read from the buffer, while the write pointer points (i.e., contains the address of) to the location where the next data value to arrive will be written. After a read or write operation is performed, the read or write pointer advances. The program must check after each advance whether the pointer has reached the last location in the buffer. If the check shows the pointer has reached the end of the buffer, the program resets the pointer to point to the first location of the buffer. Checking whether the pointer has reached the end and resetting it if it has is time-consuming. This degrades processor performance if the DSP system makes extensive use of the buffers.
To address this problem, DSP systems have used circular buffers to automatically perform the action of checking after each buffer address calculation whether the pointer has reached the end of the buffer and adjusting it relative to the buffer location if necessary.
FIG. 1
illustrates the operation of a circular buffer. The lowest address of the buffer is the base address and the highest is the end address. Thus, in
FIG. 1
the buffer is 24 in length. The index register contains the next pointer to be accessed in the buffer. In the example, the index register plus the base initially point at address
8
. If an increment of 8 is added, the next index plus the base points at address
16
. If another increment of 8 is added, the index plus the base points at address
24
. Thus, the first three memory accesses are in the buffer. However, if another increment of 8 is added, the index pointer plus base advance to address
32
. A circular buffer detects this is out of bounds and wraps the index around in the following manner. If the current index+increment−length of the buffer is less than zero (e.g., 8+8−24), the next index=current index+increment. On the other hand, if the current index+increment−length of the buffer is greater than or equal to zero (e.g., 16+8−24), the next index=current index+increment−length of the buffer. Thus, if the next index pointer plus base would point beyond the end address, the next index wraps around to be 0 and the next index plus base points at address
8
. In short, after the read pointer or the write pointer of the index register reaches the “end” of the buffer, it automatically advances to the “start” of the buffer, making the buffer appear circular to the programmer.
FIG. 2
illustrates circular buffers have significant set up overhead when performing matrix multiplication. For example, 4×4 matrix multiplication results in sixteen elements in which the top row of four elements is obtained by multiplying the top row of the left matrix by each of the four columns of the right matrix. Thus, a DSP processor reads data from the buffer of memory in the first row of the left matrix: a
00
, a
01
, a
02
, and a
03
as shown, then the left column of the right matrix: b
00
, b
10
, b
20
, and b
30
, Each of the remaining rows of the left matrix must be also multiplied by each of the four columns of the right matrix and each time the DSP processor traverses adjacent columns in the right matrix, it requires set up, which costs instructions cycles. For example, set up may require two instruction cycles to initialize the base register, load the increment register, select the format (e.g., byte, half-word, and word), and load the modulo. Thus, eight set up operations required for a 4×4 matrix will require 16 instruction cycles. If the DSP processor could directly access the columns of the right matrix, that is, transpose their addresses without set up, it would significantly boost DSP processor performance of matrix multiplication.
SUMMARY OF THE INVENTION
The invention describes systems and methods for register-indirect addressing modes used in digital signal processing systems. The invention implements both register-indirect addressing mode and modulo arithmetic to transpose the addresses. The transpose addressing mode can efficiently be used in matrix multiplication. By sharing logic used in a circular buffer, it adds a new address mode to directly access column data, which improves matrix computation. The overhead of the transpose mode is minimal by sharing the existing hardware and/or software used in circular buffers.


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