Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2002-07-01
2003-05-20
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S118000, C711S144000, C713S002000
Reexamination Certificate
active
06567899
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to computer that include cache memory and, more particularly, to a transportable memory apparatus that includes cache memory and associated methods of initializing a computer having a transportable memory apparatus.
BACKGROUND OF THE INVENTION
Generally, computers or computer systems have associated devices for storing data. The data may be stored on a relatively safe and recoverable non-volatile storage device. An example of a non-volatile storage device is a hard disk drive. The techniques or procedures for storing data on non-volatile storage devices are well known in the art. As the volume of data stored on non-volatile storage devices increases, however, so does the concern for data integrity and reliability.
When a file is written to a hard disk drive, the operating system transfers the data in the file generally in sections called blocks. A block of data is first sent to a memory controller, such as an integrated device electronics (IDE) controller or a small computer standard interface (SCSI) controller. After receiving the block of data, the controller sends an acknowledgement of receipt to the operating system. Upon receiving this acknowledgement, the operating system then considers the block to be safely stored in the storage device.
In a controller without cache memory, the memory controller transfers the data immediately to the storage device before an acknowledgement is sent back to the operating system. Many higher-end controllers have cache memories. Cache memory is higher-speed memory that stores data that has recently been retrieved from or is in the process of being transferred to a non-volatile storage device, thereby saving time by not requiring that the non-volatile storage device be accessed if the data is needed again in the near future. A memory controller (also termed a caching controller) that is associated with a cache memory sends, an acknowledgement to the operating system after the data is stored in the cache memory without waiting for the data to be stored in a non-volatile storage device.
Caching controllers generally employ one of two methods to handle data that has been written to a storage device, write-through cache and write-back cache. A caching controller employing the first method, write-through cache, writes the block of data to two locations once the data is received, that is, the caching controller writes the data to both the cache memory and to the storage device. Because the data is written to cache memory, the data can be quickly accessed again if needed for later use. However, the data is also simultaneously stored in a safe manner in the storage device. Unfortunately, the time that is required to write the data from the operating system to the storage device according to a write-through cache method is greater than the time to write data directly to a storage device without passing through a caching controller. In fact, the total time to write data according to the write-through cache method is equal to the time to write data to the cache memory plus the time to write data to a storage device.
The second method, write-back cache, reduces the time requirements of the first method by writing the block of data only to the cache memory, instead of to both cache memory and the storage device. Therefore, the total time to write data is only the time required to write data to the cache memory. However, the data will only be written from the cache memory to the non-volatile storage device when the cache memory is full or when activity on the controller is low. Unfortunately, the write-back cache method necessitates that the storage device will go through periods of not containing any new or updated blocks of data with the new or updated blocks of data being, instead, maintained by the cache memory. As such, if the power supply fails, then the new blocks of data will be lost and non-recoverable since the cache memory is volatile. This loss of data is particularly problematic since the memory controller has previously sent an acknowledgement to the operating system indicating that the data was received by the storage device without providing any indication that the data had only been stored in cache memory. Upon receiving the acknowledgment, the operating system is no longer obligated to maintain the data and therefore cannot be relied upon to recover any data lost in cache memory.
Cache memory therefore has a central flaw. When power to the caching controller fails or is interrupted for any reason, the contents of the cache memory is generally lost or corrupted. As the size of cache memories increase, the potential for data loss also increases. Numerous techniques for data recovery and data storage have been developed to overcome this problem. One such attempt to resolve this problem is to have a battery backup for the cache memory.
One example of a conventional computer system
100
that includes a cache memory system
150
is depicted in FIG.
1
. The cache memory system
150
is powered by the system power supply
130
and communicates with the computer system via system bus
115
. The cache memory system includes cache memory
200
, typically configured as a cache array, such as an Intel 21256 Dynamic Random Access Memory (DRAM). The cache memory system also includes a cache controller
160
for interacting with the central processing unit (CPU)
110
of the computer system and for generally controlling the operations of the cache memory system. As depicted in
FIG. 1
, the cache memory system also includes a refresh unit
177
that periodically refreshes the contents of the cache memory and a battery unit
176
for providing auxiliary power to the cache memory. In order to control the manner in which the cache memory is refreshed and the manner in which auxiliary power is provided to the cache memory, the cache memory system can also include a selector
180
that operates under control of the cache controller
160
. As such, the cache memory system can be designed such that the battery unit provides power to the cache memory if the system power supply fails or if power to the cache memory is otherwise interrupted. As such, the cache memory system can retain the contents of the cache memory until such time that the power failure is rectified and the computer system can again be powered on, thereby permitting the contents of the cache memory to be transferred to main memory
120
, typically a non-volatile memory device, for storage.
It is also advantageous for the cache memory
200
along with the associated battery and refresh units
176
,
177
(collectively designated as
170
in
FIG. 1
) to be modular so as to be moved from one computer system and installed in another computer system. As such, in instances in which the cache controller
160
fails while the cache memory is dirty, the battery unit can supply auxiliary power to the cache memory in order to retain the contents of the cache memory while the modular cache memory and associated battery unit are removed from the computer system that has experienced the failure and are installed in another computer system. Upon powering up the new computer system, the dirty data can be flushed from the cache memory to main memory
120
such that no data is lost.
As a result of the removal of the cache memory from a first computer system and the installation of the cache memory in a second computer system, a number of problems arise in the manner in which the second computer system is initialized so as to identify the newly installed cache memory, to detect if the newly installed cache memory has dirty data, and to appropriately flush the dirty data to a non-volatile storage device of a second computer system. If the cache memory is not identified and the dirty data is not appropriately flushed, data may be lost or the integrity of the data may otherwise be compromised, notwithstanding removal of the cache memory from the computer system that has experienced the failure and the installation of the cache memory in a different
Chatterjee Paresh
Ghosh Sukha R.
Hallyal Basavaraj Gurupadappa
Karasek Marc C.
Piper Stephen Scott
Carstens Yee & Cahoon LLP
LSI Logic Corporation
Thai Tuan V.
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