Transport subsystem for an MBIST chain architecture

Details Transport subsystem for an MBIST chain architecture Transport subsystem for an MBIST chain architecture

2008-07-31

2011-10-25

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S726000, C714S742000

Reexamination Certificate

active

08046643

ABSTRACT:
An apparatus including a controller configured to present one or more commands and receive one or more responses, a plurality of transport circuits configured to receive one of the commands, present the responses, and generate one or more control signals, and a plurality of memory-controlling circuits, each coupled to a respective one of the plurality of transport circuits and configured to generate one or more memory access signals in response to the one or more control signals, receive one or more memory output signals from a respective memory in response to the one or more memory access signals, and generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.

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