Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-03-19
2003-09-09
Le, Don (Department: 2733)
Electronic digital logic circuitry
Interface
Current driving
C326S038000, C370S401000, C370S413000
Reexamination Certificate
active
06617879
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a multi-port bridge for a local area network. More particularly, the invention relates to a transparently partitioned communication bus for interconnecting the ports of a multi-port bridge for a local area network.
BACKGROUND OF THE INVENTION
Nodes of a local area network (LAN) are typically interconnected by a shared transmission medium. The amount of data traffic that the shared transmission medium can accommodate, however, is limited. For example, only one node at a time can successfully transmit data to another node over the shared transmission medium. If two or more nodes simultaneously attempt to transmit data, a data collision occurs, which tends to corrupt the data being transmitted. Thus, nodes that share a transmission medium are considered to be in a same collision domain.
A multi-port bridge allows simultaneous communication between nodes of the LAN by segmenting the LAN into multiple collision domains (also referred to as network segments or LAN segments), each segment having a corresponding transmission medium.
FIG. 1
illustrates a conventional local area network including a multi-port bridge
10
. The multi-port bridge
10
has eight ports A-H, though the number of ports can vary. Each port A-H is connected to a segment
11
-
18
of the LAN. Each segment
11
-
18
typically includes one or more nodes
19
-
34
, such as a workstation, a personal computer, a data terminal, a file server, a printer, a facsimile, a scanner or other conventional digital device. Each of the nodes
19
-
34
has an associated node address (also referred to as a medium access control (MAC) address) which uniquely identifies the node. The nodes
19
-
34
are configured to send data, one to another, in the form of discrete data packets.
When the LAN operates according to Ethernet standards, such as the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, data is communicated in the form of discrete packets.
FIG. 2
illustrates a conventional IEEE 802.3 data packet
40
. The data packet
40
includes an eight byte long pre-amble
41
which is generally utilized for synchronizing a receiver to the data packet
40
. The pre-amble
41
includes seven bytes of pre-amble and one byte of start-of-frame. Following the pre-amble
41
, the data packet
40
includes a six-byte-long destination address
42
, which is the node address of a node which is an intended recipient for the data packet
40
. Next, the data packet
40
includes a six-byte-long source address
43
, which is the node address of a node which originated the data packet
40
. Following the source address
43
is a two-byte length field
44
. Following the length field
44
is a data field
45
. The data field
45
can be up to 1500 bytes long. Finally, the data packet
40
includes a two-byte frame check field
46
which allows a recipient of the data packet
40
to determine whether an error has occurred during transmission of the data packet
40
.
When a node (source node) sends data to another node (destination node) located on its same segment of the LAN (intra-segment communication), the data is communicated directly between the nodes without intervention by the multi-port bridge
10
and is known as an intra-segment packet. Therefore, when the multi-port bridge
10
receives an intra-segment packet, the multi-port bridge
10
does not bridge the packet (the packet is filtered). When a node (source node) sends a data packet to another node (destination node) located on a different segment (inter-segment communication), the multi-port bridge
10
appropriately forwards the data packet to the destination node.
Problems can arise, however, when the capabilities of the multi-port bridge
10
are exceeded by network demand. When data packets
40
are received by the multi-port bridge
10
at a rate that is higher than the rate at which the multi-port bridge
10
can appropriately forward each packet
40
, the multi-port bridge
10
becomes a source of network congestion. This problem is exacerbated as network users place increasing demands on the network.
Therefore, what is needed is improved technique for increasing the data packet handling capacity in a multi-port bridge for a local area network.
SUMMARY OF THE INVENTION
The invention is a transparently partitioned communication bus for interconnecting the ports of a multi-port bridge for a local area network. The communication bus is partitioned into a plurality of bus segments. Each bus segment is coupled to one or more ports of the multi-port bridge and includes a same number (n) of signal lines. One of the bus segments can be coupled to a buffer memory for temporarily storing data packets being forwarded from one port to another.
Because each bus segment is coupled to fewer than all of the ports, the signal lines of each bus segment can be physically shorter in length and less heavily loaded than if coupled to all of the ports. Accordingly, the transparently partitioned bus can transfer data in accordance with a significantly higher frequency clock signal than would otherwise be the case.
A bus control module coupled to each segment pre-charges each signal line of each bus segment to a logic high voltage level (V
CC
) by activating pre-charge transistors coupled between the voltage supply V
CC
and a plurality of diodes, each diode coupled to a corresponding one of the signal lines. Current flows from the voltage supply V
CC
to each signal line through the transistors and the respective diodes. Because the pre-charging operation includes all the signal lines of each bus segment, no combinational logic operations are required to be performed with respect to individual signal lines. As such, pre-charging of all the signal lines can be accomplished in a relatively short time period.
The ports request access to the partitioned bus from the bus control module which grants access to the partitioned bus according to an appropriate priority. A port having been granted access to the partitioned bus applies the data to be communicated to its associated bus segment by applying an appropriate logic level to each signal line of its associated bus segment. The transparent bus control module then senses the data applied by the port via sense lines coupled to each signal line of each bus segment. In the preferred embodiment, sensing of the signal lines is performed by the transparent bus control module simultaneously as the port having access to the transparent bus places data on its associated bus segment. Then, the transparent bus control module replicates this data to each other bus segment by discharging appropriate ones of the signal lines of each other bus segment via appropriate ones of a plurality of discharge transistors. The discharge transistors are coupled to between each signal line of each bus segment and ground. This technique results in the data being replicated to the other bus segments in a relatively short period of time.
Accordingly, the bus is “transparently” partitioned such that the bus segments, in conjunction with the transparent bus control module, form a single logical bus by which the ports communicate data. A principle advantage of this aspect of the present invention is that the entire bus cycle can be made shorter than a bus cycle for a non-partitioned bus.
According to an aspect of the present invention, an apparatus having a partitioned bus for transferring data includes a first bus segment having a first plurality of (n) signal lines; a second bus segment having a second plurality of (n) signal lines; conditioning means coupled to the first bus segment for conditioning a logic level of each signal line of the first bus segment according to data to be transferred; sensing means coupled to the first bus segment for sensing a logic level of each signal line of the first bus segment, pre-charging means coupled to the second bus segment for pre-charging each signal line of the second bus segment; and dis-charging means coupled to the second bus segment for dis-charging selected ones of the sig
Haverstock & Owens LLP
Le Don
Sony Corporation
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