Transparent SDRAM in an embedded environment

Details Transparent SDRAM in an embedded environment Transparent SDRAM in an embedded environment

2006-11-21

2006-11-21

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S168000, C711S169000, C711S170000

Reexamination Certificate

active

07139893

ABSTRACT:
A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.

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patent: 2002/0078316 (2002-06-01), Nakamura

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