Transparent re-mapping of parallel computational units

Details Transparent re-mapping of parallel computational units Transparent re-mapping of parallel computational units

2007-09-18

2007-09-18

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10942334

ABSTRACT:
An design architecture for an application specific integrated circuit (ASIC) is disclosed. The design architecture of the ASIC includes a pre-determined number of redundant computational units such that when defective computational units are found during testing, full functionality of the ASIC is maintained by re-mapping functionality from the defective units to the once redundant units. The marking of defective units and the re-mapping of functionality are automated by using self-test logic built into each computational unit in the ASIC. The self-test logic is adapted to allow the corresponding computational unit to self-isolate itself from the data initialization process and to self-disable to avoid any computation when the ASIC is in operation mode. The re-mapping of functionality is achieved by initializing the computational units in the array in a serial manner.

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European Search Report; Application No. EP 05 25 5651; Feb. 8, 2006; 5 pages; European Patent Office.

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