Transparent management at host interface of flash-memory overhea

Details Transparent management at host interface of flash-memory overhea Transparent management at host interface of flash-memory overhea

1997-09-29

1999-09-21

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

714773, G06F 1108

Patent

active

059567430

ABSTRACT:
A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code when stored in the flash-memory chips. A DRAM cache stores the pages of data as enlarged pages with the overhead bytes, even though the enlarged pages are not aligned to a power of 2. When an enlarged page is read out of a flash-memory chip, its ECC code is immediately checked and the ECC code in the overhead bytes is replaced with a syndrome code and stored in the DRAM cache. A local processor for the flash-memory system then reads the syndrome code in the overhead bytes and repairs any error using repair information in the syndrome. The overhead bytes are stripped off when pages are transferred from the DRAM cache to a host. The host can be notified early by an intermediate interrupt after a programmable number of pages have been read. This improves performance since the host does not have to wait for an entire block of pages to be read.

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