Transparent level 2 cache controller

Details Transparent level 2 cache controller Transparent level 2 cache controller

2011-05-24

2011-05-24

Patel, Kaushikkumar (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S122000

Reexamination Certificate

active

07949833

ABSTRACT:
A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.

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