Transparent error correction code memory system and method

Details Transparent error correction code memory system and method Transparent error correction code memory system and method

2006-10-03

2006-10-03

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C365S201000

Reexamination Certificate

active

07117421

ABSTRACT:
The present invention provides flexible and efficient memory configuration that is capable of economically addressing both resource consumption and ECC concerns. A memory system facilitates transparent ECC operations without dedicated ECC connections. A first dynamic random access memory structure stores data, wherein the data connections to the memory system are limited to the width of the first dynamic random access memory structure. A second dynamic random access memory structure dedicated to storing error correction code information, wherein the error correction code information is accessed via the data connections. In one exemplary implementation, the first memory structure and the second memory structure the data and ECC are included in the same memory bank. In an alternate implementation, the first memory structure and the second memory structure the data and ECC are included in the different memory banks and are accessed in parallel.

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