Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-09-25
2007-09-25
Baker, Stephen M. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S773000
Reexamination Certificate
active
11221098
ABSTRACT:
A high-speed partial-word write operation is performed in a memory system. First, an error correction code (ECC) word, which includes a data word and associated error correction bits, is read from a memory array. A word line and a plurality of sense amplifiers are enabled during this read operation. The read data word is corrected in response to the associated error correction bits, thereby creating a corrected data word. The corrected data word is merged with a write data word, thereby creating a merged write data word. Write error correction bits are generated in response to the merged write data word, and the merged write data word and write error correction bits are written to the memory array. The word line and the plurality of sense amplifiers remain enabled from the reading operation through the write operation, thereby speeding up the partial-word write operation.
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Baker Stephen M.
Bever Hoffman & Harms LLP
Hoffman E. Eric
Monolithic System Technology, Inc.
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