Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-23
2003-11-25
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S151000, C438S155000, C438S711000, C438S715000, C438S720000, C438S742000
Reexamination Certificate
active
06653216
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating an active matrix substrate in a display panel or the like, and an apparatus for forming a transparent electrode in the matrix substrate.
Active matrix substrates using thin film transistors are often used as active matrix substrates for use in conventional liquid crystal display panels or the like. Such active matrix substrates are usually fabricated by forming a plurality of active matrix constructions on a transparent plate having a size corresponding to a plurality of display panels and separating the plate into individual active matrix substrates, by cutting.
FIGS. 18 and 19
show examples of equivalent circuit plan views of one display panel when such display panels are formed on a glass plate having a size corresponding to a plurality of display panels.
This active matrix substrate includes a glass plate
1
having a size corresponding to a plurality of display panels. The surface of this glass plate
1
has a display region
5
for displaying an image and a non-display region
6
which is formed outside the display region
5
and does not display images. After the active matrix constructions are formed, the glass plate
1
is cut along cut lines
2
to separate the display panel units. That is, the region inside the cut lines
2
is a panel formation region
3
, and the region outside this panel formation region
3
is a surplus region
4
. Lattice-like short lines
15
are formed on this surplus region
4
. In the display region
5
, a plurality of pixel electrodes
7
and a plurality of thin film transistors
8
connected with these pixel electrodes
7
are formed in a matrix manner. A plurality of scan lines
9
supply a scan signal to gates G of the thin film transistors
8
. A plurality of data lines
10
formed on the glass substrate supply a display signal to drain electrodes D of the thin film transistors
8
. This display region
5
also includes a plurality of auxiliary capacitor lines
11
for forming auxiliary capacitors Cs between these auxiliary capacitor lines
11
and the pixel electrodes
7
, and a protect ring
12
formed around the pixel electrodes
7
. In the construction shown in
FIG. 18
, the right end portion of each auxiliary capacitor line
11
is connected to the short line
15
via a common line
24
and a connecting pad
25
formed outside the right edge of the protect ring
12
. As shown in
FIG. 19
, each auxiliary capacitor line
11
is sometimes connected to the protect ring
12
and then connected to the short line
15
via the connecting pad
25
. Outside the protect ring
12
, a scan line protective element
13
is formed for each scan line
9
, and a data line protective element
14
is formed for each data line
10
. The scan line protective element
13
includes two thin film transistors
13
a
and
13
b
inserted between the protect ring
12
and the scan line
9
. The data line protective element
14
includes two thin film transistors
14
a
and
14
b
inserted between the protect ring
12
and the data line
10
. These protective elements
13
and
14
prevent insulation breakdown of the thin film transistor
8
caused by high-voltage static electricity generated during the fabrication process or prevent changes in the voltage-current characteristics.
The left end portion of each scan line
9
is connected to the short line
15
via a scan line connecting pad
17
formed in a scan line driving semiconductor chip mounting region
16
in the non-display region
6
. The upper end portion of each data line
10
is connected to the short line
15
via a data line connecting pad
19
formed in a data line driving semiconductor chip mounting region
18
in the non-display region
6
. Input connecting pads
20
formed in the semiconductor chip mounting region
16
and input connecting pads
21
formed in the semiconductor chip mounting region
18
are connected, via lines
23
, to external connecting terminals
22
which are to be connected to an external control circuit and the like. These external connecting terminals
22
are further connected to the short line
15
.
Both of a gate electrode G and a source electrode S of the thin film transistor
13
a
of the scan line protective element
13
including two thin film transistors are connected to the scan line
9
. A drain electrode D of this thin film transistor
13
a
is connected to the protect ring
12
. A gate electrode G and a source electrode S of the other thin film transistor
13
b
are connected together to the protect ring
12
. A drain electrode D of this thin film transistor
13
b
is connected to the scan line
9
. Both of a gate electrode G and a source electrode S of the thin film transistor
14
a
of the data line protective element
14
including two thin film transistors are connected to the protect ring
12
. A drain electrode D of this thin film transistor
14
a
is connected to the data line
10
. A gate electrode G and a source electrode S of the other thin film transistor
14
b
are connected together to the data line
10
. A drain electrode D of this thin film transistor
14
b
is connected to the protect ring
12
.
In the active matrix substrate with the above construction, the source and drain electrodes of the thin film transistors and the data lines are usually formed at the same time by using the same material. To reduce the contact resistance between the source electrode S of the thin film transistor and the pixel electrode
7
made of Indium-Tin-Oxide (ITO), the drain electrodes D and the source electrodes S of the thin film transistors and the data lines
10
are often formed by a metal film made of a metal, such as Cr (Chromium), Ti (Titanium), Ta (Tantalum), or Mo (Molybdenum), which has a higher oxidation-reduction potential than that of an Al (Aluminum) alloy (to be referred to as an Al-based metal hereinafter) and hence is more sparingly oxidizable than an Al-based metal. When any of such metals is used, the contact resistance between the source electrode S and the ITO pixel electrode
7
reduces. However, since these metals are high-resistance metals, the resistance of the data line
10
increases if the width of the data line
10
decreases, and this increases the wiring time constant. Accordingly, the width of the data line
10
cannot unlimitedly be decreased, so the opening ratio is difficult to increase. To prevent this, therefore, the source and drain electrodes of the thin film transistors and the data lines are formed by a two-layered structure including a Cr layer and an Al-based metal layer and connected to the ITO pixel electrodes
7
via this Cr layer. Consequently, the Cr layer reduces the contact resistance, and the Al-based metal layer reduces the data line resistance. A structure as shown in a sectional view of
FIG. 20
is known as an active matrix substrate having this arrangement. This active matrix substrate is fabricated by forming steps as shown in FIG.
21
. Note that the thin film transistors constructing the protective elements
13
and
14
are formed in substantially the same manner as the thin film transistors
8
, so a detailed description thereof will be omitted.
First, in step P
1
(metal film formation step) shown in
FIG. 21
, a film of Al (aluminum) or an Al-based metal is formed on the upper surface of a glass plate
1
. In step P
2
(first photoresist formation step) shown in
FIG. 21
, a first photoresist film is formed on the upper surface of this Al-based metal film. In step P
3
(scan line and the like formation step) shown in
FIG. 21
, this first photoresist film is used as a mask to selectively etch the Al-based metal film, thereby forming, e.g., a gate electrode G for a thin film transistor
8
, a scan line
9
, a lower metal layer
17
a
for a connecting pad
17
, an auxiliary capacitor line
11
, upper and lower edges
12
a
for a protect ring
12
, a line
23
, and a lower metal layer
22
a
for an external connecting terminal
22
.
In step P
4
(three film formation step) shown in
FIG. 21
, a gate insulating film
Higashi Toshiaki
Ishii Hiromitsu
Miyagawa Makoto
Nakamura Yayoi
Shimomaki Shinichi
Casio Computer Co. Ltd.
Frishauf Holtz Goodman & Chick P.C.
Malsawma Lex H.
Smith Matthew
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