Transmitting command block data using the lower address part of

Details Transmitting command block data using the lower address part of Transmitting command block data using the lower address part of

1998-03-14

2000-07-04

Follansbee, John A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

G06F 1340

Patent

active

060852720

ABSTRACT:
Apparatus and methods are defined for increasing the effective bandwidth of a system bus for commanding a co-processor in an information processing system. The system processor commands the co-processor by sending a command block including one or more command parameters via the system bus. The bus includes an address phase and a data phase, and the effective bus bandwidth is increased by using a significant portion of the address phase and all of the data phase for sending the command parameters. The system processor disassembles the parameters and packs these into the address portion and the data phase of as few bus transfer commands as required. The co-processor includes a front end which receives the command and uses the command to select an appropriate procedure for unpacking and reassembling the received command parameters. Previous methods have transferred the command parameters using only the data phase of the system bus transfers. The increase in effective bandwidth is proportional to the ratio of the total number of bus transfers previously required to the total number required using the teachings of the invention.

REFERENCES:
patent: 5274784 (1993-12-01), Arimilli et al.
patent: 5638520 (1997-06-01), Moyer
patent: 5706478 (1998-01-01), Dye
patent: 5734849 (1998-03-01), Butcher
patent: 5944805 (1999-08-01), Ricks et al.

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