Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-09-07
2003-10-21
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C326S063000
Reexamination Certificate
active
06636071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to, for example, a transmitting circuit that transmits a logic signal to a receiving circuit of which the power supply voltage is different, a receiving circuit, a transmitting-receiving circuit, and an electro-optical apparatus in which these circuits are used.
2. Description of Related Art
Generally, in an electro-optical apparatus, for example, in a liquid crystal panel, an element substrate on which a non-linear element, a pixel electrode and the likes are formed, and an opposite substrate on which an opposite electrode (or a common electrode) that is opposite to the pixel electrode is formed, are pasted together while maintaining a certain gap with the electrode surfaces thereof opposing each other. A liquid crystal as an electro-optical material is sandwiched between this gap. Herein, in the element substrate, when using a 3-terminal type element such as a TFT (Thin Film Transistor) and the like as a non-linear element, and in the element substrate and the opposite substrate, when using a 2-terminal type element such as a TFD (Thin Film Diode) and the like as a non-linear element, at the respective peripheral areas other than at the pasted areas, a driving circuit (driver IC) is installed by the COG (Chip On Glass) technique, thereby reducing the number of connecting points in the liquid crystal panel.
SUMMARY OF THE INVENTION
Since an external control circuit is generally constituted of a CMOS circuit, an amplitude of its logic signal is about 3 to 5 V. On the other hand, in order to drive the non-linear element and/or the liquid crystal, a relatively higher voltage of about 20 V is required. As such, because the operational voltage ranges of both circuits are different from each other, it is more convenient from the view point of design that the power supply voltage of the logic signal in the external control circuit and the power supply voltage of the driving circuit be separated each other in the arrangement.
However, with this arrangement, it is not possible to supply the logic signal of the external control circuit to the driving circuit directly. Therefore, conventionally, as shown in
FIG. 18
, a logic signal is output from a buffer
410
constituting an output stage of the external control circuit through a capacitor
500
, and then is supplied to the buffer
610
constituting an input stage of the driving circuit indirectly. That is, in the arrangement as shown in
FIG. 18
, for the power supply voltage of the buffer
410
in the external control circuit, the voltage V
1
and the ground potential GND are used, but for the power supply voltage of the buffer
610
in the driving circuit, voltage V
2
and voltage V
3
are used. Herein, V
1
−GND=V
2
−V
3
. Further, D
1
and D
2
represent the protection diodes.
Incidentally, from the external control circuit to a connection point of the liquid crystal panel, an FPC (Flexible Printed Circuit) substrate is used for wiring, and on the other hand, from the connection point of the liquid crystal panel to the driving circuit, a transparent conductor such as ITO (Indium Tin Oxide) deposited on the substrate is patterned for wiring. Herein, Rx represents the wiring resistance of the transparent conductor and Cx represents the stray capacitance of the transparent conductor. Furthermore, for generalizing the description, it is assumed that the external control circuit is to be the transmitting circuit
400
in a sense of transmitting the logic signal, and the driving circuit is to be the receiving circuit
600
in a sense of receiving the logic signal.
However, the wiring resistance Rx of the transparent conductor such as ITO is much larger than the resistance of a copper foil of the FPC substrate. Further, since the wiring pitch of the transparent conductor is extremely narrow, the stray capacitance Cx thereof can not be ignored. Accordingly, as a result, with these wiring resistance Rx and the stray capacitance Cx, the signal waveform at the input point B in the receiving circuit
600
(the input signal waveform of the buffer
610
) becomes, as shown in
FIG. 19
, dull in comparison to the signal waveform at the output point A in the transmitting circuit
400
(the output signal waveform of the buffer
410
), and the delay time &Dgr;T of the output signal from the buffer
610
becomes longer than the signal at the output point A. Further, because a signal amplitude at the input point B becomes smaller than the voltage “V
2
-V
3
”, the noise margin &agr; of the peak value and the threshold value of the buffer
610
decreases, and thus there is a problem that in the worst case, a malfunction will also occur.
The present invention is made in light of at least the above described problem, and one object of the present invention is to provide a transmitting circuit for transmitting a logic signal that prevents a malfunction on the circuit side, even if the wiring resistance and the stray capacitance increase on a receiving circuit side (the other party of the logic signal), a receiving circuit, a transmitting-receiving circuit, and an electro-optical apparatus that uses these circuits.
An exemplary embodiment according to the present application is a transmitting circuit for transmitting a logic signal to a receiving circuit through a capacitor. The amplitude voltage of the logic signal to be transmitted is made larger than the power supply voltage to the logic element that receives the logic signal in the receiving circuit. As a result thereof, since the amplitude of the logic signal to be received in the receiving circuit is expanded, the delay time may be shortened and there may be room in the noise margin. Further, according to this arrangement, there is no need to modify the arrangement on the receiving circuit side.
The transmitting circuit of this exemplary embodiment preferably consists of a level shifter for expanding the amplitude voltage of the logic signal to be transmitted. With this arrangement, a relatively simpler arrangement is feasible, while separately requiring a different power supply voltage for simply operating the level shifter on the receiving circuit side.
The transmitting circuit of this exemplary embodiment may include a holding element for holding a predetermined voltage. The level shifter is preferably a logic element in which a voltage, to or from which the predetermined voltage being held in the holding element is added or subtracted, is set to be the power supply voltage. According to this arrangement, the predetermined voltage is set-up as a result thereof, and with the logic element which sets the predetermined voltage as the power supply thereof, an expansion of the amplitude of the logic signal to be transmitted is attempted. Further, as the predetermined voltage, the power supply voltage of the logic circuit placed at the front stage of the level shifter is appropriate. As a result, a single power supply voltage in the transmitting circuit will be sufficient.
On the other hand, to expand the amplitude of the logic signal to be transmitted other than with the level shifter, an arrangement including a holding element for holding a predetermined voltage is considered in which a voltage being held in the holding element is added to or subtracted from one of the levels of the logic signal to be transmitted. With such arrangement, it is possible to expand the amplitude of the logic signal in the receiving circuit by a single power supply voltage.
Another exemplary embodiment according to the present application is a receiving circuit for receiving a logic signal transmitted from a transmitting circuit through a capacitor. The power supply voltage to the logic element to which the received logic signal is input is made smaller than the amplitude voltage of the logic signal transmitted from the transmitting circuit. Accordingly, this arrangement is may be maintained without modifying the arrangement on the transmitting circuit side.
The receiving circuit of this exemplary embodiment preferably furthe
Le Don
Seiko Epson Corporation
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